yT8rl(r4$rockchip,rk3328-evbrockchip,rk3328 +7Rockchip RK3328 EVBaliases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000i/ethernet@ff540000s/ethernet@ff550000cpus+cpu@0}cpuarm,cortex-a53arm,armv8xpscicpu@1}cpuarm,cortex-a53arm,armv8xpscicpu@2}cpuarm,cortex-a53arm,armv8xpscicpu@3}cpuarm,cortex-a53arm,armv8xpsci l2-cache0cacheopp_table0operating-points-v2opp-408000000Q~#@4opp-600000000#F~#@opp-8160000000,B@#@opp-1008000000<#@opp-1200000000G(#@opp-1296000000M?d #@amba simple-bus+@dmac@ff1f0000arm,pl330arm,primecell@G Rapb_pclk^ arm-pmuarm,cortex-a53-pmu0Gdefgi psciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer0G   xin24m fixed-clock|n6xin24m2i2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s G)7Ri2s_clki2s_hclk txrx disabledi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s G*8Ri2s_clki2s_hclk  txrx disabledi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s G+9Ri2s_clki2s_hclk txrx disabledspdif@ff030000rockchip,rk3328-spdif G.: Rmclkhclk txdefault  disabledpdm@ff040000 rockchip,pdm=RRpdm_clkpdm_hclk rxdefaultsleep  disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd+1io-domains"rockchip,rk3328-io-voltage-domain disabledpower-controller!rockchip,rk3328-power-controller+pd_hevc@6pd_video@5pd_vpu@8reboot-modesyscon-reboot-modeRB RBRB )RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart G7&Rbaudclkapb_pclk  txrxdefault 5B disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart G8'Rbaudclkapb_pclk  txrxdefault 5B disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart G9(Rbaudclkapb_pclk  txrxdefault5Bokayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c G$+7 Ri2cpclkdefault disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c G%+8 Ri2cpclkdefaultokaypmic@18rockchip,rk805 G|xin32krk805-clkout2L\default h!!!!""regulatorsDCDC_REG1 vdd_logic 4 2regulator-state-memD\B@DCDC_REG2vdd_arm 4 2regulator-state-memD\~DCDC_REG3vcc_ddr2regulator-state-memDDCDC_REG4vcc_io2Z2Z2"regulator-state-memD\2ZLDO_REG1vcc_18w@w@2regulator-state-memD\w@LDO_REG2 vcc18_emmcw@w@2regulator-state-memD\w@LDO_REG3vdd_10B@B@2regulator-state-memD\B@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c G&+9 Ri2cpclkdefault# disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c G'+: Ri2cpclkdefault$ disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi G1+ Rspiclkapb_pclk  txrxdefault%&'( disabledwatchdog@ff1a0000 snps,dw-wdt G(pwm@ff1b0000rockchip,rk3328-pwm< Rpwmpclkdefault)x disabledpwm@ff1b0010rockchip,rk3328-pwm< Rpwmpclkdefault*x disabledpwm@ff1b0020rockchip,rk3328-pwm < Rpwmpclkdefault+x disabledpwm@ff1b0030rockchip,rk3328-pwm0 G2< Rpwmpclkdefault,x disabledthermal-zonessoc-thermal-tripstrip-point0ppassivetrip-point1Lpassive.soc-crits criticalcooling-mapsmap0. tsadc@ff250000rockchip,rk3328-tsadc% G:$P$Rtsadcapb_pclkinitdefaultsleep/0&/0B 7tsadc-apbC1Pgokay-efuse@ff260000rockchip,rk3328-efuse&P+> Rpclk_efuse} id@7cpu-leakage@17logic-leakage@19cpu-version@1aadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc( GP%Rsaradcapb_pclk0V 7saradc-apb disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-4500TGZW]XY[\"gpgpmmupppp0ppmmu0pp1ppmmu1 Rbuscore0fiommu@ff330200rockchip,iommu3 G` h265e_mmu Raclkiface disablediommu@ff340800rockchip,iommu4@ Gb vepu_mmuF Raclkiface disablediommu@ff350800rockchip,iommu5@ G vpu_mmuF Raclkiface disablediommu@ff360480rockchip,iommu 6@6@ GJ rkvdec_mmuB Raclkiface disablediommu@ff373f00rockchip,iommu7? G vop_mmu; Raclkiface disabledclock-controller@ff440000(rockchip,rk3328-crurockchip,crusysconDC1|x=&'(ABDC"\5H4$z222|n6n6n6n6#FLGрxhxhрxhxhsyscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfdE+usb2-phy@100rockchip,rk3328-usb2phy2Rphyclk usb480m_phy|{3okay3otg-port$G;<=otg-bvalidotg-idlinestateokayDhost-port G> linestateokayEdwmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcP@ G  =!JNRbiuciuciu-driveciu-sampleрokay ):default4567E8dwmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcQ@ G  >"KORbiuciuciu-driveciu-sampleрokay )Q^t9default :;<dwmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcR@ G ?#LPRbiuciuciu-driveciu-sampleрokay default =>?ethernet@ff540000rockchip,rk3328-gmacT Gmacirq8dWXZYMRstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac0c 7stmmacethC1 disabledethernet@ff550000rockchip,rk3328-gmacUC1 Gmacirq8TSSUVIRstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphy0bd7stmmacethmac-phyrmii@okayAoutputeTmdiosnps,dwmac-mdio+phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22V0ddefaultBC@usb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2X GMRotgotg@ !D &usb2-phyokayusb@ff5c0000 generic-ehci\ G N3 Rusbhostutmi!E&usbokayusb@ff5d0000 generic-ohci] G N3 Rusbhostutmi!E&usbokayinterrupt-controller@ff811000 arm,gic-4000A@ @ `  G pinctrlrockchip,rk3328-pinctrlC1+@gpio0@ff210000rockchip,gpio-bank! G3L\A0Sgpio1@ff220000rockchip,gpio-bank" G4L\A0Rgpio2@ff230000rockchip,gpio-bank# G5L\A0gpio3@ff240000rockchip,gpio-bank$ G6L\A0pcfg-pull-upVHpcfg-pull-downcPpcfg-pull-nonerFpcfg-pull-none-2marOpcfg-pull-up-2maVpcfg-pull-up-4maVIpcfg-pull-none-4marLpcfg-pull-down-4macpcfg-pull-none-8marJpcfg-pull-up-8maVKpcfg-pull-none-12mar Mpcfg-pull-up-12maV Npcfg-output-highpcfg-output-lowpcfg-input-highVGpcfg-inputi2c0i2c0-xfer FFi2c1i2c1-xfer FFi2c2i2c2-xfer  FF#i2c3i2c3-xfer FF$i2c3-gpio FFhdmi_i2chdmii2c-xfer FFpdm-0pdmm0-clkF pdmm0-fsyncFpdmm0-sdi0F pdmm0-sdi1Fpdmm0-sdi2Fpdmm0-sdi3Fpdmm0-clk-sleepGpdmm0-sdi0-sleepGpdmm0-sdi1-sleepGpdmm0-sdi2-sleepGpdmm0-sdi3-sleepGpdmm0-fsync-sleepGtsadcotp-gpio F/otp-out F0uart0uart0-xfer  FHuart0-cts Fuart0-rts Fuart0-rts-gpio Fuart1uart1-xfer FHuart1-ctsFuart1-rtsFuart1-rts-gpioFuart2-0uart2m0-xfer FHuart2-1uart2m1-xfer FHspi0-0spi0m0-clkHspi0m0-cs0 Hspi0m0-tx Hspi0m0-rx Hspi0m0-cs1 Hspi0-1spi0m1-clkHspi0m1-cs0Hspi0m1-txHspi0m1-rxHspi0m1-cs1Hspi0-2spi0m2-clkH%spi0m2-cs0H(spi0m2-txH&spi0m2-rxH'i2s1i2s1-mclkFi2s1-sclkFi2s1-lrckrxFi2s1-lrcktxFi2s1-sdiFi2s1-sdoFi2s1-sdio1Fi2s1-sdio2Fi2s1-sdio3Fi2s1-sleepGGGGGGGGGi2s2-0i2s2m0-mclkFi2s2m0-sclkFi2s2m0-lrckrxFi2s2m0-lrcktxFi2s2m0-sdiFi2s2m0-sdoFi2s2m0-sleep`GGGGGGi2s2-1i2s2m1-mclkFi2s2m1-sclkFi2sm1-lrckrxFi2s2m1-lrcktxFi2s2m1-sdiFi2s2m1-sdoFi2s2m1-sleepPGGGGGspdif-0spdifm0-txFspdif-1spdifm1-txFspdif-2spdifm2-txF sdmmc0-0sdmmc0m0-pwrenIsdmmc0m0-gpioIsdmmc0-1sdmmc0m1-pwrenIsdmmc0m1-gpioITsdmmc0sdmmc0-clkJ4sdmmc0-cmdK5sdmmc0-dectnI6sdmmc0-wrprtIsdmmc0-bus1Ksdmmc0-bus4@KKKK7sdmmc0-gpioIIIIIIIIsdmmc0extsdmmc0ext-clkLsdmmc0ext-cmdIsdmmc0ext-wrprtIsdmmc0ext-dectnIsdmmc0ext-bus1Isdmmc0ext-bus4@IIIIsdmmc0ext-gpioIIIIIIIIsdmmc1sdmmc1-clk J<sdmmc1-cmd K;sdmmc1-pwrenKsdmmc1-wrprtKsdmmc1-dectnKsdmmc1-bus1Ksdmmc1-bus4@KKKK:sdmmc1-gpio I IIIIIIIIemmcemmc-clkM=emmc-cmdN>emmc-pwrenFemmc-rstnoutFemmc-bus1Nemmc-bus4@NNNNemmc-bus8NNNNNNNN?pwm0pwm0-pinF)pwm1pwm1-pinF*pwm2pwm2-pinF+pwmirpwmir-pinF,gmac-1rgmiim1-pins` J LLJLLL L LJ JLLJJJ JLJJJJrmiim1-pinsOMOOOO O OM M F FFFFFgmac2phyfephyled-speed100Ffephyled-speed10Ffephyled-duplexFfephyled-rxm0Ffephyled-txm0Ffephyled-linkm0Ffephyled-rxm1FBfephyled-txm1Ffephyled-linkm1FCtsadc_pintsadc-int Ftsadc-gpio Fhdmi_pinhdmi-cecFhdmi-hpdPcif-0dvp-d2d9-m0FFFFF F F FFFFFcif-1dvp-d2d9-m1FFFFFFFFFFFFpmicpmic-int-lH sdio-pwrseqwifi-enable-hFQchosenserial2:1500000n8dc-12vregulator-fixeddc_12v2Usdio-pwrseqmmc-pwrseq-simpledefaultQ R9sdmmc-regulatorregulator-fixed SdefaultTvcc_sd2Z2Z"8vcc-sysregulator-fixedvcc_sys2LK@LK@U!vcc-phy-regulatorregulator-fixedvcc_phy2A compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1device_typeregclocks#cooling-cellsdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrangesinterruptsclock-names#dma-cellsinterrupt-affinity#clock-cellsclock-frequencyclock-output-namesdmasdma-namesstatuspinctrl-namespinctrl-0pinctrl-1#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftgpio-controller#gpio-cellsrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cells#reset-cellsassigned-clock-parents#phy-cellsfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablephy-modephy-handlephy-supplyclock_in_outassigned-clock-ratephy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dmaphysphy-names#interrupt-cellsinterrupt-controllerbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathreset-gpiosgpiovin-supply