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#address-cells#size-cellsmodelcompatiblegpio0gpio1serial0serial1interrupts-extendedcontrollerinterrupt-parentpcie-mem-aperturepcie-io-aperturerangesregclocksstatuscache-unifiedcache-levelarm,double-linefill-incrarm,double-linefill-wraparm,double-linefillprefetch-datainterrupts#interrupt-cellsinterrupt-controllerphandlepinctrl-namespinctrl-0gpio-controller#gpio-cellsreg-shiftreg-io-widthmarvell,pinsmarvell,functionreg-namesngpios#pwm-cells#clock-cells#phy-cellsmsi-controllerclock-namestx-csum-limitphy-modespeedfull-duplexphydmacap,memcpydmacap,xordmacap,memsetmarvell,reg-initdsa,memberlabelethernetmarvell,crypto-sramsmarvell,crypto-sram-sizeinternal-memclock-output-namesmrvl,clk-delay-cyclesbus-widthno-1-8-vnon-removableno-memory-wccell-indexspi-max-frequencydevice_typemsi-parentbus-rangeassigned-addressesinterrupt-map-maskinterrupt-mapmarvell,pcie-portmarvell,pcie-laneclock-frequencyenable-methodstdout-path