V\8P(PT$,rockchip,rk3229-evbrockchip,rk3229!7Rockchip RK3229 Evaluation boardaliases=/serial@11010000E/serial@11020000M/serial@11030000U/spi@11090000cpuscpu@f00Zcpu,arm,cortex-a7fjq@pscicpu@f01Zcpu,arm,cortex-a7fjqpscicpu@f02Zcpu,arm,cortex-a7fjqpscicpu@f03Zcpu,arm,cortex-a7fjqpsciopp_table0,operating-points-v2opp-408000000Q~@opp-600000000#Fopp-8160000000,B@opp-1008000000<opp-1200000000Gtxopp-1296000000M?d7opp-1392000000R<opp-1464000000WB\amba ,simple-buspdma@110f0000,arm,pl330arm,primecellf@ $apb_pclk arm-pmu,arm,cortex-a7-pmu0LMNO0psci,arm,psci-1.0arm,psci-0.2smctimer,arm,armv7-timerC0   gn6oscillator ,fixed-clockgn6wxin24m!i2s1@100b0000(,rockchip,rk3228-i2srockchip,rk3066-i2sf @ $i2s_clki2s_hclkQ  txrxdefault  disabledi2s0@100c0000(,rockchip,rk3228-i2srockchip,rk3066-i2sf @ $i2s_clki2s_hclkP txrx disabledspdif@100d0000,rockchip,rk3228-spdiff  S $mclkhclk txdefault  disabledi2s2@100e0000(,rockchip,rk3228-i2srockchip,rk3066-i2sf@ $i2s_clki2s_hclkR txrx disabledsyscon@11000000&,rockchip,rk3228-grfsysconsimple-mfdf"io-domains",rockchip,rk3228-io-voltage-domainokay   usb2-phy@760,rockchip,rk3228-usb2phyf` $phyclk wusb480m_phy0okay2otg-port$;<=otg-bvalidotg-idlinestateokay1host-port > linestateokay 3usb2-phy@800,rockchip,rk3228-usb2phyf $phyclk wusb480m_phy1okay4otg-port D linestateokay 5host-port E linestateokay 6serial@11010000,snps,dw-apb-uartf 7gn6MU$baudclkapb_pclkdefault  disabledserial@11020000,snps,dw-apb-uartf 8gn6NV$baudclkapb_pclkdefault disabledserial@11030000,snps,dw-apb-uartf 9gn6OW$baudclkapb_pclkdefaultokayefuse@11040000,rockchip,rk3228-efusef G $pclk_efuseid@7fcpu_leakage@17fi2c@11050000,rockchip,rk3228-i2cf $$i2cLdefault disabledi2c@11060000,rockchip,rk3228-i2cf %$i2cMdefault disabledi2c@11070000,rockchip,rk3228-i2cf &$i2cNdefault disabledi2c@11080000,rockchip,rk3228-i2cf '$i2cOdefault disabledspi@11090000,rockchip,rk3228-spif  1AR$spiclkapb_pclkdefault disabledwatchdog@110a0000 ,snps,dw-wdtf  (b disabledpwm@110b0000,rockchip,rk3288-pwmf ,^$pwmdefault disabledpwm@110b0010,rockchip,rk3288-pwmf ,^$pwmdefaultokayBpwm@110b0020,rockchip,rk3288-pwmf ,^$pwmdefaultokayCpwm@110b0030,rockchip,rk3288-pwmf 0,^$pwmdefault  disabledtimer@110c0000,,rockchip,rk3228-timerrockchip,rk3288-timerf  + !a $timerpclkclock-controller@110e0000,rockchip,rk3228-cruf7"DHQkb$a#g0,eррxhррxhthermal-zonescpu-thermalvd#tripscpu_alert0papassive$cpu_alert1$apassive%cpu_crit_ acriticalcooling-mapsmap0$ map1% tsadc@11150000,rockchip,rk3228-tsadcf :HX$tsadcapb_pclkQHajW tsadc-apbinitdefaultsleep&'& sokay"#gpu@20000000",rockchip,rk3228-maliarm,mali-400f Hgpgpmmupp0ppmmu0pp1ppmmu1 $buscorej~ disablediommu@20020800,rockchip,iommuf   vpu_mmu $aclkiface9 disablediommu@20030480,rockchip,iommuf @ @  vdec_mmu $aclkiface9 disablediommu@20053f00,rockchip,iommuf ?  vop_mmu $aclkiface9 disablediommu@20070800,rockchip,iommuf  iep_mmu $aclkiface9 disableddwmmc@300000000,rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcf0@   Drv$biuciuciu-driveciu-sampleEdefault ()* disableddwmmc@300100000,rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcf0@   Esw$biuciuciu-driveciu-sampleEdefault +,- disableddwmmc@300200000,rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcf0@ g<4`P<4` Guy$biuciuciu-driveciu-sample^hEdefault ./0jSresetokay}usb@300400002,rockchip,rk3228-usbrockchip,rk3066-usbsnps,dwc2f0 $otgotg@ 1 usb2-phyokayusb@30080000 ,generic-ehcif0  2 $usbhostutmi3usbokayusb@300a0000 ,generic-ohcif0   2 $usbhostutmi3usbokayusb@300c0000 ,generic-ehcif0   4 $usbhostutmi5usbokayusb@300e0000 ,generic-ohcif0  4 $usbhostutmi5usbokayusb@30100000 ,generic-ehcif0 B 46usb $usbhostutmiokayusb@30120000 ,generic-ohcif0 C 4 $usbhostutmi6usbokayethernet@30200000,rockchip,rk3228-gmacf0  macirq8~oM$stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macj8 stmmaceth7"okayQ}~ 7}input 8rgmiidefault9 &:6 L'B@a0jinterrupt-controller@32010000 ,arm,gic-400s f22 2@ 2`   pinctrl,rockchip,rk3228-pinctrl7"gpio0@11110000,rockchip,gpio-bankf 3@sgpio1@11120000,rockchip,gpio-bankf 4Asgpio2@11130000,rockchip,gpio-bankf 5Bs:gpio3@11140000,rockchip,gpio-bankf 6Cs>pcfg-pull-up=pcfg-pull-downpcfg-pull-none<pcfg-pull-none-drv-12ma ;sdmmcsdmmc-clk;(sdmmc-cmd;)sdmmc-bus4@;;;;*sdiosdio-clk;+sdio-cmd;,sdio-bus4@;;;;-emmcemmc-clk<.emmc-cmd</emmc-bus8<<<<<<<<0gmacrgmii-pins< <<;;;; ; ;<<<< <<9rmii-pins< <<;; ;<<<<phy-pins <<i2c0i2c0-xfer <<i2c1i2c1-xfer <<i2c2i2c2-xfer <<i2c3i2c3-xfer <<spi0spi0-clk =spi0-cs0=spi0-tx =spi0-rx =spi0-cs1 =spi1spi1-clk=spi1-cs0=spi1-rx=spi1-tx=spi1-cs1=i2s1i2s1-bus< < < < <<<<< pwm0pwm0-pin<pwm1pwm1-pin<pwm2pwm2-pin <pwm3pwm3-pin < spdifspdif-tx< tsadcotp-gpio<&otp-out<'uart0uart0-xfer <<uart0-cts<uart0-rts<uart1uart1-xfer  < <uart1-cts<uart1-rts <uart2uart2-xfer =<uart21-xfer  = <uart2-cts<uart2-rts<keyspwr-key=Dusbhost-vbus-drv<?memory@60000000Zmemoryf`@dc-12v-regulator,regulator-fixeddc_12v 0HAext_gmac ,fixed-clockgsY@ wext_gmac7vcc-host-regulator,regulator-fixed` 1>default? vcc_host s@vcc-phy-regulator,regulator-fixed`vcc_phy0w@Hw@ s 8vcc-sys-regulator,regulator-fixedvcc_sys 0LK@HLK@sA@vccio-1v8-regulator,regulator-fixed vccio_1v80w@Hw@ s@ vccio-3v3-regulator,regulator-fixed vccio_3v302ZH2Z s@ vdd-arm-regulator,pwm-regulator~Ba@vdd_arm0~H\ vdd-log-regulator,pwm-regulator~Ca@vdd_log0B@H  gpio_keys ,gpio-keysdefaultDpower-keyGPIO Key Power >td #address-cells#size-cellsinterrupt-parentcompatiblemodelserial0serial1serial2spi0device_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksenable-methodcpu-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrangesinterrupts#dma-cellsclock-namesinterrupt-affinityarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsdmasdma-namespinctrl-namespinctrl-0statusvccio1-supplyvccio2-supplyvccio4-supplyinterrupt-names#phy-cellsphy-supplyreg-shiftreg-io-width#pwm-cellsrockchip,grf#reset-cellsassigned-clocksassigned-clock-ratespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereset-namespinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-modeiommu-cellsfifo-depthmax-frequencybus-widthdefault-sample-phasecap-mmc-highspeeddisable-wpnon-removabledr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dmaphysphy-namesassigned-clock-parentsclock_in_outphy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltenable-active-highvin-supplypwmspwm-supplyautorepeatlabelgpioslinux,codedebounce-intervalwakeup-source