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ĹstmmacethŃě€Bokay$rgmii-'mdio0ethernet-phy@0†1>KXer ¸~‹ ¸›'gpio@ff708000!snps,dw-apb-gpio†˙p€&( Bdisabledgpio-controller@0!snps,dw-apb-gpio-port—§ł†ăŇ ´¤gpio@ff709000!snps,dw-apb-gpio†˙p&(Bokaygpio-controller@0!snps,dw-apb-gpio-port—§ł†ăŇ ´Ľ›,gpio@ff70a000!snps,dw-apb-gpio†˙p &( Bdisabledgpio-controller@0!snps,dw-apb-gpio-port—§ł†ăŇ ´Śi2c@ffc04000!snps,designware-i2c†˙Ŕ@#,&) ´žBokayeeprom@51 !atmel,24c32†QÁ rtc@68!dallas,ds1339†hi2c@ffc05000!snps,designware-i2c†˙ŔP#-&) ´Ÿ Bdisabledi2c@ffc06000!snps,designware-i2c†˙Ŕ`#.&) ´  Bdisabledi2c@ffc07000!snps,designware-i2c†˙Ŕp#/&) ´Ą Bdisabledeccmgr!altr,socfpga-ecc-managerřl2-ecc@ffd08140!altr,socfpga-l2-ecc†˙Ё@´$%ocram-ecc@ffd08144!altr,socfpga-ocram-ecc†˙ЁDĘ*´˛łcache-controller@fffef000!arm,pl310-cache†˙ţđ ´&ĎÝ é ů ';Oh“›l3regs@0xff800000!altr,l3regssyscon†˙€dwmmc0@ff704000!altr,socfpga-dw-mshc†˙p@ ´‹ &(+-biuciuBokay§ąťÍ Ţ,ç-ó-nand@ff900000!altr,socfpga-denali-nand†˙˙¸nand_datadenali_reg ´ ˙˙˙˙&. Bdisabledsram@ffff0000 !mmio-sram†˙˙›*spi@ff705000!cdns,qspi-nor†˙pP˙  ´—€#3&/Bokayn25q512a@0 !n25q512a†HőáZixˆ˜2Ś2´Ârstmgr@ffd05000Đ !altr,rst-mgr†˙ĐPÝ›#snoop-control-unit@fffec000!arm,cortex-a9-scu†˙ţŔsdr@ffc25000!altr,sdr-ctlsyscon†˙ÂP›0sdramedac!altr,sdram-edacđ0 ´'spi@fff00000!snps,dw-apb-ssi†˙đ ´š&1 Bdisabledspi@fff01000!snps,dw-apb-ssi†˙đ ´›&1 Bdisabledsysmgr@ffd08000!altr,sys-mgrsyscon†˙Ѐ@˙ЀÄ›$timer@fffec600!arm,cortex-a9-twd-timer†˙ţĆ ´ &2timer0@ffc08000!snps,dw-apb-timer ´§†˙Ŕ€&)-timertimer1@ffc09000!snps,dw-apb-timer ´¨†˙Ŕ&)-timertimer2@ffd00000!snps,dw-apb-timer ´Š†˙Đ& -timertimer3@ffd01000!snps,dw-apb-timer ´Ş†˙Đ& -timerserial0@ffc02000!snps,dw-apb-uart†˙Ŕ  ´˘!&).333txrxserial1@ffc03000!snps,dw-apb-uart†˙Ŕ0 ´Ł!&).333txrxusbphy=!usb-nop-xceivBokay›5usb@ffb00000 !snps,dwc2†˙°˙˙ ´}&4-otg#"Ĺdwc2H5 Musb2-phy Bdisabledusb@ffb40000 !snps,dwc2†˙´˙˙ ´€&4-otg##Ĺdwc2H5 Musb2-phyBokaywatchdog@ffd02000 !snps,dw-wdt†˙Đ  ´Ť& Bokaywatchdog@ffd03000 !snps,dw-wdt†˙Đ0 ´Ź&  Bdisabledchosen Wearlyprintk`serial0:115200n8memory@0zmemory†@3-3-v-regulator!regulator-fixedl3.3V{2Z “2Z ›-gpio-leds !gpio-ledshps_led0Ťhps:green:led0 ť, hps_led1Ťhps:green:led1 ť, hps_led2Ťhps:green:led2 ť,hps_led3Ťhps:green:led3 ť, #address-cells#size-cellsmodelcompatibleethernet0ethernet1serial0serial1timer0timer1timer2timer3enable-methoddevice_typeregnext-level-cachephandleinterrupt-parentinterruptsinterrupt-affinity#interrupt-cellsinterrupt-controllerranges#dma-cells#dma-channels#dma-requestsclocksclock-namesfpga-mgrstatus#clock-cellsclock-frequencydiv-regfixed-dividerclk-gateclk-phaseresetsaltr,sysmgr-sysconinterrupt-namesmac-addressreset-namessnps,multicast-filter-binssnps,perfect-filter-entriestx-fifo-depthrx-fifo-depthphy-modephyrxd0-skew-psrxd1-skew-psrxd2-skew-psrxd3-skew-psrxdv-skew-psrxc-skew-pstxen-skew-pstxc-skew-psgpio-controller#gpio-cellssnps,nr-gpiospagesizeiramcache-unifiedcache-levelarm,tag-latencyarm,data-latencyprefetch-dataprefetch-instrarm,shared-overridearm,double-linefillarm,double-linefill-incrarm,double-linefill-wraparm,prefetch-droparm,prefetch-offsetbroken-cdbus-widthcap-mmc-highspeedcap-sd-highspeedcd-gpiosvmmc-supplyvqmmc-supplyreg-namesdma-maskcdns,fifo-depthcdns,fifo-widthcdns,trigger-addressspi-max-frequencym25p,fast-readcdns,page-sizecdns,block-sizecdns,read-delaycdns,tshsl-nscdns,tsd2d-nscdns,tchsh-nscdns,tslch-ns#reset-cellsaltr,modrst-offsetaltr,sdr-sysconnum-cscpu1-start-addrreg-shiftreg-io-widthdmasdma-names#phy-cellsphysphy-namesbootargsstdout-pathregulator-nameregulator-min-microvoltregulator-max-microvoltlabel