Đ ţíO0HI (HŘsamtec VIN|ING FPGA1!samtec,viningaltr,socfpga-cyclone5altr,socfpgaaliases,/soc/ethernet@ff7020006/soc/ethernet@ff700000@/soc/serial0@ffc02000H/soc/serial1@ffc03000P/soc/timer0@ffc08000W/soc/timer1@ffc09000^/soc/timer2@ffd00000e/soc/timer3@ffd01000cpuslaltr,socfpga-smpcpu@0!arm,cortex-a9zcpu†Š›cpu@1!arm,cortex-a9zcpu†Š›pmu@ff111000!arm,cortex-a9-pmuŁ´°ąż†˙˙0intc@fffed000!arm,cortex-a9-gicŇă†˙ţĐ˙ţÁ›soc !simple-buszsocŁřamba !simple-busřpdma@ffe01000!arm,pl330arm,primecell†˙ŕ`´hijklmno˙  & -apb_pclk›2base_fpga_region !fpga-region9can@ffc00000 !bosch,d_can†˙Ŕ0´ƒ„…†& Bdisabledcan@ffc01000 !bosch,d_can†˙Ŕ0´‡ˆ‰Š& Bdisabledclkmgr@ffd04000 !altr,clk-mgr†˙Đ@clocksosc1I !fixed-clockV}x@› osc2I !fixed-clock› f2s_periph_ref_clkI !fixed-clock› f2s_sdram_ref_clkI !fixed-clock›main_pll@40I!altr,socfpga-pll-clock& †@› mpuclk@48I!altr,socfpga-perip-clk&  fŕ †H›mainclk@4cI!altr,socfpga-perip-clk&  fä †L›dbg_base_clk@50I!altr,socfpga-perip-clk&  fč †P›main_qspi_clk@54I!altr,socfpga-perip-clk& †T›main_nand_sdmmc_clk@58I!altr,socfpga-perip-clk& †X›cfg_h2f_usr0_clk@5cI!altr,socfpga-perip-clk& †\›periph_pll@80I!altr,socfpga-pll-clock & †€› emac0_clk@88I!altr,socfpga-perip-clk& †ˆ›emac1_clk@8cI!altr,socfpga-perip-clk& †Œ›per_qsi_clk@90I!altr,socfpga-perip-clk& †›per_nand_mmc_clk@94I!altr,socfpga-perip-clk& †”›per_base_clk@98I!altr,socfpga-perip-clk& †˜›h2f_usr1_clk@9cI!altr,socfpga-perip-clk& †œ›sdram_pll@c0I!altr,socfpga-pll-clock & †Ŕ›ddr_dqs_clk@c8I!altr,socfpga-perip-clk&†Č›ddr_2x_dqs_clk@ccI!altr,socfpga-perip-clk&†Ě› ddr_dq_clk@d0I!altr,socfpga-perip-clk&†Đ›!h2f_usr2_clk@d4I!altr,socfpga-perip-clk&†Ô›"mpu_periph_clkI!altr,socfpga-perip-clk&n›1mpu_l2_ram_clkI!altr,socfpga-perip-clk&nl4_main_clkI!altr,socfpga-gate-clk&|`›l3_main_clkI!altr,socfpga-perip-clk&nl3_mp_clkI!altr,socfpga-gate-clk& fd|`›l3_sp_clkI!altr,socfpga-gate-clk& fdl4_mp_clkI!altr,socfpga-gate-clk& fd|`›)l4_sp_clkI!altr,socfpga-gate-clk& fd|`›*dbg_at_clkI!altr,socfpga-gate-clk& fh|`›dbg_clkI!altr,socfpga-gate-clk& fh|`dbg_trace_clkI!altr,socfpga-gate-clk& fl|`dbg_timer_clkI!altr,socfpga-gate-clk&|`cfg_clkI!altr,socfpga-gate-clk&|`h2f_user0_clkI!altr,socfpga-gate-clk&|` emac_0_clkI!altr,socfpga-gate-clk&| ›%emac_1_clkI!altr,socfpga-gate-clk&| ›&usb_mp_clkI!altr,socfpga-gate-clk&|  f¤›3spi_m_clkI!altr,socfpga-gate-clk&|  f¤›0can0_clkI!altr,socfpga-gate-clk&|  f¤›can1_clkI!altr,socfpga-gate-clk&|  f¤ ›gpio_db_clkI!altr,socfpga-gate-clk&|  f¨h2f_user1_clkI!altr,socfpga-gate-clk&| sdmmc_clkI!altr,socfpga-gate-clk & | …‡›sdmmc_clk_dividedI!altr,socfpga-gate-clk&| n›,nand_x_clkI!altr,socfpga-gate-clk & |  ›-nand_clkI!altr,socfpga-gate-clk & |  nqspi_clkI!altr,socfpga-gate-clk & |  ›.ddr_dqs_clk_gateI!altr,socfpga-gate-clk&|Řddr_2x_dqs_clk_gateI!altr,socfpga-gate-clk& |Řddr_dq_clk_gateI!altr,socfpga-gate-clk&!|Řh2f_user2_clkI!altr,socfpga-gate-clk&"|Řfpga_bridge@ff400000!altr,socfpga-lwhps2fpga-bridge†˙@#a&fpga_bridge@ff500000!altr,socfpga-hps2fpga-bridge†˙P#`&fpgamgr@ff706000!altr,socfpga-fpga-mgr†˙p`˙š ´Ż›ethernet@ff7000000!altr,socfpga-stmmacsnps,dwmac-3.70asnps,dwmac –$`†˙p  ´sŠmacirqš&% -stmmaceth#  ĹstmmacethŃě€ Bdisabledethernet@ff7020000!altr,socfpga-stmmacsnps,dwmac-3.70asnps,dwmac –$`†˙p  ´xŠmacirqš&& -stmmaceth#! ĹstmmacethŃě€Bokay$rgmii-' 8(H ^'''mdio0!snps,dwmac-mdioethernet-phy@1†s€š§´ (ŔÍĐ›'gpio@ff708000!snps,dw-apb-gpio†˙p€&)Bokaygpio-controller@0!snps,dw-apb-gpio-portŮéő†ăŇ ´¤›(gpio@ff709000!snps,dw-apb-gpio†˙p&)Bokaygpio-controller@0!snps,dw-apb-gpio-portŮéő†ăŇ ´Ľ›6gpio@ff70a000!snps,dw-apb-gpio†˙p &)Bokaygpio-controller@0!snps,dw-apb-gpio-portŮéő†ăŇ ´Ś›5i2c@ffc04000!snps,designware-i2c†˙Ŕ@#,&* ´žBokaypca9557@1f !nxp,pca9557†Ůélm75@48!lm75†Hat24@50 !atmel,24c01†Pi2cswitch@70 !nxp,pca9548†pi2c@0†i2c@1†i2c@2†i2c@3†i2c@4†i2c@5†i2c@6†eeprom@51 !atmel,24c01†Qi2c@7†eeprom@51 !atmel,24c01†Qi2c@ffc05000!snps,designware-i2c†˙ŔP#-&* ´ŸBokayV† at24@50 !atmel,24c02†Pi2c@ffc06000!snps,designware-i2c†˙Ŕ`#.&* ´  Bdisabledi2c@ffc07000!snps,designware-i2c†˙Ŕp#/&* ´Ą Bdisabledeccmgr!altr,socfpga-ecc-managerřl2-ecc@ffd08140!altr,socfpga-l2-ecc†˙Ё@´$%ocram-ecc@ffd08144!altr,socfpga-ocram-ecc†˙ЁD +´˛łcache-controller@fffef000!arm,pl310-cache†˙ţđ ´& + ;LZi}‘ŞĂŐ›l3regs@0xff800000!altr,l3regssyscon†˙€dwmmc0@ff704000!altr,socfpga-dw-mshc†˙p@ ´‹ &),-biuciu Bdisabledéóýnand@ff900000!altr,socfpga-denali-nand†˙˙¸ nand_datadenali_reg ´*˙˙˙˙&- Bdisabledsram@ffff0000 !mmio-sram†˙˙›+spi@ff705000!cdns,qspi-nor†˙pP˙  ´—3€CS&.Bokayn25q128@0!n25q128†hőáz‰˜¨¸2Ć2Ôân25q00@1!n25q00†hőáz‰˜¨¸2Ć2Ôârstmgr@ffd05000đ !altr,rst-mgr†˙ĐPý›#snoop-control-unit@fffec000!arm,cortex-a9-scu†˙ţŔsdr@ffc25000!altr,sdr-ctlsyscon†˙ÂP›/sdramedac!altr,sdram-edac/ ´'spi@fff00000!snps,dw-apb-ssi†˙đ ´š &0 Bdisabledspi@fff01000!snps,dw-apb-ssi†˙đ ´› &0 Bdisabledsysmgr@ffd08000!altr,sys-mgrsyscon†˙Ѐ@'˙ЀÄ›$timer@fffec600!arm,cortex-a9-twd-timer†˙ţĆ ´ &1timer0@ffc08000!snps,dw-apb-timer ´§†˙Ŕ€&*-timertimer1@ffc09000!snps,dw-apb-timer ´¨†˙Ŕ&*-timertimer2@ffd00000!snps,dw-apb-timer ´Š†˙Đ& -timertimer3@ffd01000!snps,dw-apb-timer ´Ş†˙Đ& -timerserial0@ffc02000!snps,dw-apb-uart†˙Ŕ  ´˘7A&*N22Stxrxserial1@ffc03000!snps,dw-apb-uart†˙Ŕ0 ´Ł7A&*N22Stxrxusbphy]!usb-nop-xceivBokay›4usb@ffb00000 !snps,dwc2†˙°˙˙ ´}&3-otg#"Ĺdwc2h4 musb2-phyBokaywhostusb@ffb40000 !snps,dwc2†˙´˙˙ ´€&3-otg##Ĺdwc2h4 musb2-phyBokay wperipheralwatchdog@ffd02000 !snps,dw-wdt†˙Đ  ´Ť& Bokaywatchdog@ffd03000 !snps,dw-wdt†˙Đ0 ´Ź&  Bdisabledchosenconsole=ttyS0,115200memory@0zmemory†@gpio-keys !gpio-keyshps_temp0ˆBTN_0 ý5Žhps_hkey0ˆBTN_1 ý5Žhps_hkey1 ˆhps_hkey1 ý5Žtregulator-usb-nrst!regulator-fixed ™usb_nrst¨LK@ŔLK@ C6Řpéü #address-cells#size-cellsmodelcompatibleethernet0ethernet1serial0serial1timer0timer1timer2timer3enable-methoddevice_typeregnext-level-cachephandleinterrupt-parentinterruptsinterrupt-affinity#interrupt-cellsinterrupt-controllerranges#dma-cells#dma-channels#dma-requestsclocksclock-namesfpga-mgrstatus#clock-cellsclock-frequencydiv-regfixed-dividerclk-gateclk-phaseresetsaltr,sysmgr-sysconinterrupt-namesmac-addressreset-namessnps,multicast-filter-binssnps,perfect-filter-entriestx-fifo-depthrx-fifo-depthphy-modephy-handlesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usrxd0-skew-psrxd1-skew-psrxd2-skew-psrxd3-skew-pstxen-skew-pstxc-skew-psrxdv-skew-psrxc-skew-psgpio-controller#gpio-cellssnps,nr-gpiospagesizeiramcache-unifiedcache-levelarm,tag-latencyarm,data-latencyprefetch-dataprefetch-instrarm,shared-overridearm,double-linefillarm,double-linefill-incrarm,double-linefill-wraparm,prefetch-droparm,prefetch-offsetbroken-cdbus-widthcap-mmc-highspeedcap-sd-highspeedreg-namesdma-maskcdns,fifo-depthcdns,fifo-widthcdns,trigger-addressspi-max-frequencym25p,fast-readcdns,page-sizecdns,block-sizecdns,read-delaycdns,tshsl-nscdns,tsd2d-nscdns,tchsh-nscdns,tslch-ns#reset-cellsaltr,modrst-offsetaltr,sdr-sysconnum-cscpu1-start-addrreg-shiftreg-io-widthdmasdma-names#phy-cellsphysphy-namesdr_modebootargslabellinux,coderegulator-nameregulator-min-microvoltregulator-max-microvoltstartup-delay-usenable-active-highregulator-always-on