8( .firefly,firefly-rk3288-reloadrockchip,rk3288&7Firefly-RK3288-reloadaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/dwmmc@ff0f0000k/dwmmc@ff0c0000q/dwmmc@ff0d0000w/dwmmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12'@5< Hcpu@501cpuarm,cortex-a12'@5Hcpu@502cpuarm,cortex-a12'@5Hcpu@503cpuarm,cortex-a12'@5Hcpu-opp-tableoperating-points-v2PHopp-126000000[b opp-216000000[ b opp-312000000[b opp-408000000[Qb opp-600000000[#Fb opp-696000000[)|b~opp-816000000[0,bB@opp-1008000000[<bopp-1200000000[Gbopp-1416000000[TfrbOopp-1512000000[ZJb opp-1608000000[_"bpamba simple-buspdma-controller@ff250000arm,pl330arm,primecell%@w5 apb_pclkH dma-controller@ff600000arm,pl330arm,primecell`@w5 apb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@w5 apb_pclkHfreserved-memorypdma-unusable@fe000000oscillator fixed-clockn6xin24mH timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H 5a  pclktimerdisplay-subsystemrockchip,display-subsystem dwmmc@ff0c0000rockchip,rk3288-dw-mshc!р 5Drvbiuciuciu-driveciu-sample/  @:resetokayFPbsdefault dwmmc@ff0d0000rockchip,rk3288-dw-mshc!р 5Eswbiuciuciu-driveciu-sample/ ! @:resetokayFbdefaultdwmmc@ff0e0000rockchip,rk3288-dw-mshc!р 5Ftxbiuciuciu-driveciu-sample/ "@:reset disableddwmmc@ff0f0000rockchip,rk3288-dw-mshc!р 5Guybiuciuciu-driveciu-sample/ #@:resetokayFP(defaultsaradc@ff100000rockchip,saradc $75I[saradcapb_pclkW :saradc-apbokayHspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi5ARspiclkapb_pclkI Ntxrx ,default!"#$ disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi5BSspiclkapb_pclkI Ntxrx -default%&'( disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi5CTspiclkapb_pclkI  Ntxrx .default)*+, disabledi2c@ff140000rockchip,rk3288-i2c >i2c5Mdefault- disabledi2c@ff150000rockchip,rk3288-i2c ?i2c5Odefault. disabledi2c@ff160000rockchip,rk3288-i2c @i2c5Pdefault/ disabledi2c@ff170000rockchip,rk3288-i2c Ai2c5Qdefault0okayH|serial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 7Xb5MUbaudclkapb_pclkdefault 123okayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 8Xb5NVbaudclkapb_pclkdefault4okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 9Xb5OWbaudclkapb_pclkdefault5okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :Xb5PXbaudclkapb_pclkdefault6okayserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;Xb5QYbaudclkapb_pclkdefault7 disabledthermal-zonesreserve_thermalo8cpu_thermalod8tripscpu_alert0ppassiveH9cpu_alert1$passiveH:cpu_crit_ criticalcooling-mapsmap09 map1: gpu_thermalod8tripsgpu_alert0ppassiveH;gpu_crit_ criticalcooling-mapsmap0; tsadc@ff280000rockchip,rk3288-tsadc( %5HZtsadcapb_pclk :tsadc-apbinitdefaultsleep<=<sokay&H8ethernet@ff290000rockchip,rk3288-gmac)Amacirqeth_wake_irqQ>85fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB :stmmacethok^n?inputdefault@ABCDrgmii 'B@ E0usb@ff500000 generic-ehciP 5usbhostFusb disabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 5otghostG usb2-phyokaydefaultHusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 5otgotg +@@ I usb2-phyokayusb@ff5c0000 generic-ehci\ 5usbhost disabledi2c@ff650000rockchip,rk3288-i2ce <i2c5LdefaultJokaysyr827@40silergy,syr827:@Wvdd_cpuf P~p,@KH syr828@41silergy,syr828:AWvdd_gpuf P~pKact8846@5aactive-semi,act8846ZdefaultLMKK&K1K<KHKTNregulatorsREG1Wvcc_ddrfO~OREG2Wvcc_iof2Z~2ZHREG3Wvdd_logf~REG4Wvcc_20f~HNREG5 Wvccio_sdf2Z~2ZHREG6 Wvdd10_lcdfB@~B@REG7Wvcca_18fw@~w@REG8Wvcca_33f2Z~2ZHRREG9 Wvcca_lanf2Z~2ZHDREG10Wvdd_10fB@~B@REG11Wvcc_18fw@~w@HREG12 Wvcc18_lcdfw@~w@hym8563@51haoyu,hym8563Qxin32k&OdefaultPHi2c@ff660000rockchip,rk3288-i2cf =i2c5NdefaultQokayes8328@10everest,es8328`RlRxRR5Ri2s_hclki2s_clkpwm@ff680000rockchip,rk3288-pwmhdefaultS5^pwm disabledpwm@ff680010rockchip,rk3288-pwmhdefaultT5^pwm disabledpwm@ff680020rockchip,rk3288-pwmh defaultU5^pwm disabledpwm@ff680030rockchip,rk3288-pwmh0defaultV5^pwm disabledbus_intmem@ff700000 mmio-srampppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsHpower-controller!rockchip,rk3288-power-controller^hn Hipower-domain@9 5chgfdehilkj$WXYZ[\]^_power-domain@11 5op`apower-domain@12 5bpower-domain@13 5cdreboot-modesyscon-reboot-modeRBRBRB RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruvQ>H^jk$#gׄeрxhрxhHsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwH>edp-phyrockchip,rk3288-dp-phy5h24m disabledHyio-domains"rockchip,rk3288-io-voltage-domainokay!.8eCQD_m}usbphyrockchip,rk3288-usb-phyokayusb-phy@320 5]phyclkHIusb-phy@33445^phyclkHFusb-phy@348H5_phyclkHGwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt5p Ookaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif hclkmclk5TIfNtx 6defaultgQ>okayHi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s 5IffNtxrxi2s_hclki2s_clk5Rdefaulthokaycypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 5}aclkhclksclkapb_pclk :crypto-rstokayiommu@ff900800rockchip,iommu@ Aiep_mmu5 aclkiface disablediommu@ff914000rockchip,iommu @P Aisp_mmu5 aclkiface disabledrga@ff920000rockchip,rk3288-rga 5jaclkhclksclki ilm :coreaxiahbvop@ff930000rockchip,rk3288-vop 5aclk_vopdclk_vophclk_vopi def :axiahbdclkjokayportH endpoint@0&kH~endpoint@1&lHzendpoint@2&mHtendpoint@3&nHwiommu@ff930300rockchip,iommu  Avopb_mmu5 aclkifacei okayHjvop@ff940000rockchip,rk3288-vop 5aclk_vopdclk_vophclk_vopi  :axiahbdclkookayportH endpoint@0&pHendpoint@1&qH{endpoint@2&rHuendpoint@3&sHxiommu@ff940300rockchip,iommu  Avopl_mmu5 aclkifacei okayHomipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ 5~d refpclki Q> disabledportsportendpoint@0&tHmendpoint@1&uHrlvds@ff96c000rockchip,rk3288-lvds@5g pclk_lvdslcdcvi Q> disabledportsport@0endpoint@0&wHnendpoint@1&xHsdp@ff970000rockchip,rk3288-dp@ b5icdppclkydpo:dpQ> disabledportsport@0endpoint@0&zHlendpoint@1&{Hqhdmi@ff980000rockchip,rk3288-dw-hdmibQ> g5hmniahbisfrceci okay6|default}portsportendpoint@0&~Hkendpoint@1&Hpiommu@ff9a0800rockchip,iommu Avpu_mmu5 aclkiface disablediommu@ff9c0440rockchip,iommu @@@ o Ahevc_mmu5 aclkiface disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ Ajobmmugpu5i  disabledgpu-opp-tableoperating-points-v2Hopp-100000000[b~opp-200000000[ b~opp-300000000[bB@opp-400000000[ׄbopp-500000000[ebOopp-600000000[#Fbqos@ffaa0000syscon Hcqos@ffaa0080syscon Hdqos@ffad0000syscon HXqos@ffad0100syscon HYqos@ffad0180syscon HZqos@ffad0400syscon H[qos@ffad0480syscon H\qos@ffad0500syscon HWqos@ffad0800syscon H]qos@ffad0880syscon H^qos@ffad0900syscon H_qos@ffae0000syscon Hbqos@ffaf0000syscon H`qos@ffaf0080syscon Hainterrupt-controller@ffc01000 arm,gic-400BW@ @ `   Hefuse@ffb40000rockchip,rk3288-efuse 5q pclk_efusecpu_leakage@17pinctrlrockchip,rk3288-pinctrlQ>pgpio0@ff750000rockchip,gpio-banku Q5@hxBWHgpio1@ff780000rockchip,gpio-bankx R5AhxBWgpio2@ff790000rockchip,gpio-banky S5BhxBWgpio3@ff7a0000rockchip,gpio-bankz T5ChxBWgpio4@ff7b0000rockchip,gpio-bank{ U5DhxBWHEgpio5@ff7c0000rockchip,gpio-bank| V5EhxBWgpio6@ff7d0000rockchip,gpio-bank} W5FhxBWgpio7@ff7e0000rockchip,gpio-bank~ X5GhxBWHOgpio8@ff7f0000rockchip,gpio-bank Y5HhxBWHhdmihdmi-cec-c0H}hdmi-cec-c7hdmi-ddc pcfg-pull-upHpcfg-pull-downHpcfg-pull-noneHpcfg-pull-none-12ma Hsuspendglobal-pwroffddrio-pwroffddr0-retentionddr1-retentionedpedp-hpd i2c0i2c0-xfer HJi2c1i2c1-xfer H-i2c2i2c2-xfer   HQi2c3i2c3-xfer H.i2c4i2c4-xfer H/i2c5i2c5-xfer H0i2s0i2s0-bus`Hhlcdclcdc-ctl@Hvsdmmcsdmmc-clkH sdmmc-cmdHsdmmc-cdHsdmmc-bus1sdmmc-bus4@Hsdmmc-pwr Hsdio0sdio0-bus1sdio0-bus4@Hsdio0-cmdHsdio0-clkHsdio0-cdsdio0-wpsdio0-pwrsdio0-bkpwrsdio0-intHsdio1sdio1-bus1sdio1-bus4@sdio1-cdsdio1-wpsdio1-bkpwrsdio1-intsdio1-cmdsdio1-clksdio1-pwr emmcemmc-clkHemmc-cmdHemmc-pwr Hemmc-bus1emmc-bus4@emmc-bus8Hspi0spi0-clk H!spi0-cs0 H$spi0-txH"spi0-rxH#spi0-cs1spi1spi1-clk H%spi1-cs0 H(spi1-rxH'spi1-txH&spi2spi2-cs1spi2-clkH)spi2-cs0H,spi2-rxH+spi2-tx H*uart0uart0-xfer H1uart0-ctsH2uart0-rtsH3uart1uart1-xfer  H4uart1-cts uart1-rts uart2uart2-xfer H5uart3uart3-xfer H6uart3-cts uart3-rts uart4uart4-xfer H7uart4-cts uart4-rts tsadcotp-gpio H<otp-out H=pwm0pwm0-pinHSpwm1pwm1-pinHTpwm2pwm2-pinHUpwm3pwm3-pinHVgmacrgmii-pins H@rmii-pinsphy-int HCphy-pmebHBphy-rstHAspdifspdif-tx Hgpcfg-output-highHpcfg-output-lowHpcfg-pull-up-drv-12ma Hact8846pwr-holdHMpmic-vselHLirir-intdvpdvp-pwr Hcif-pwr Hhym8563rtc-intHPkeyspwr-keyHledspower-ledHwork-ledHsdiowifi-enableHusb_hosthost-vbus-drvHusbhub-rstHHusb_otgotg-vbus-drv Hmemory@0memoryexternal-gmac-clock fixed-clocksY@ ext_gmacH?flash-regulatorregulator-fixed Wvcc_flashfw@~w@Hadc-keys adc-keysbuttonsw@button-recovery Recovery h )gpio-keys gpio-keyspower C Q GPIO Power tdefaultir-receivergpio-ir-receiver QOleds gpio-ledspower Q firefly:blue:powerdefault Wwork Q firefly:blue:user grc-feedbackdefaultsdio-pwrseqmmc-pwrseq-simple5 ext_clockdefault }EHsoundsimple-audio-card SPDIFsimple-audio-card,dai-link@1cpu codec spdif-outlinux,spdif-ditHusb-host-regulatorregulator-fixed  default Wvcc_host_5vfLK@~LK@Kvsys-regulatorregulator-fixedWvcc_5vfLK@~LK@HKsdmmc-regulatorregulator-fixed O defaultWvcc_sdf2Z~2Z Husb-otg-regulatorregulator-fixed   default Wvcc_otg_5vfLK@~LK@Kdovdd-1v8-regulatorregulator-fixed   default Wdovdd_1v8fw@~w@Hevcc28-dvp-regulatorregulator-fixed   default Wvcc28_dvpf*~*af_28-regulatorregulator-fixed  O default Wdvdd_1v2fO~Owifi-regulatorregulator-fixedWvbat_wlf2Z~2ZH #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclockscpu0-supplyphandleopp-sharedopp-hzopp-microvoltranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendportsmax-frequencyfifo-depthreset-namesbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wppinctrl-namespinctrl-0vmmc-supplyvqmmc-supplycap-sdio-irqmmc-pwrseqnon-removablesd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-ddr50mmc-ddr-1_8vmmc-hs200-1_8v#io-channel-cellsdmasdma-namesreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-active-lowsnps,reset-delays-ussnps,reset-gpiotx_delayrx_delayphysphy-namesdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizefcs,suspend-voltage-selectorregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-enable-ramp-delayregulator-ramp-delayvin-supplysystem-power-controllervp1-supplyvp2-supplyvp3-supplyvp4-supplyinl1-supplyinl2-supplyinl3-supplyDVDD-supplyAVDD-supplyPVDD-supplyHPVDD-supply#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsaudio-supplybb-supplydvp-supplyflash0-supplyflash1-supplygpio30-supplygpio1830-supplylcdc-supplysdcard-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointddc-i2c-businterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowio-channelsio-channel-nameskeyup-threshold-microvoltlabellinux,codepress-threshold-microvoltwakeup-sourcegpiospanic-indicatorlinux,default-triggerreset-gpiossimple-audio-card,namesound-daienable-active-highstartup-delay-us