8( j`2logicpd,dm3730-som-lv-devkitti,omap3630ti,omap3 ++7LogicPD Zoom DM3730 SOM-LV Development Kitchosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/mmc@4809c000Q/ocp@68000000/mmc@480b4000V/ocp@68000000/mmc@480ad000[/ocp@68000000/serial@4806a000c/ocp@68000000/serial@4806c000k/ocp@68000000/serial@49020000s/ocp@68000000/serial@49042000 {/display@0cpus+cpu@0arm,cortex-a8cpucpus 'O 57pmu@54000000arm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bush +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus + pinmux@30 ti,omap3-padconfpinctrl-single08+#A^defaultlvpinmux_mm3_pins0~468:vpinmux_mcbsp2_pins ~ vpinmux_uart2_pins(~DFHJhvpinmux_mcspi1_pins ~vpinmux_hsusb2_pins0~      vpinmux_hsusb_otg_pins`~rtvxz|~v pinmux_i2c1_pins~vpinmux_i2c2_pins~vpinmux_i2c3_pins~vpinmux_tsc2004_pins~Vvpinmux_twl4030_pins~Avpinmux_gpio_key_pins~vpinmux_led_pins~.vpinmux_lan9221_pins~Tvpinmux_mmc1_pins@~vpinmux_lcd_enable_pin~Zvpinmux_dss_dpi_pins1~vscm_conf@270sysconsimple-busp0+ p0vpbias_regulator@2b0ti,pbias-omap3ti,pbias-omappbias_mmc_omap2430pbias_mmc_omap2430w@-vclocks+mcbsp5_mux_fck@68ti,composite-mux-clockhv mcbsp5_fckti,composite-clock vmcbsp1_mux_fck@4ti,composite-mux-clockv mcbsp1_fckti,composite-clock vmcbsp2_mux_fck@4ti,composite-mux-clock vmcbsp2_fckti,composite-clock vmcbsp3_mux_fck@68ti,composite-mux-clock hvmcbsp3_fckti,composite-clockvmcbsp4_mux_fck@68ti,composite-mux-clock hvmcbsp4_fckti,composite-clockvclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \+#A^defaultlpinmux_hsusb1_reset_pin~vpinmux_wl127x_gpio_pin~  vpinmux_twl4030_vpins ~vpinmux_led_pins_wkup~$vpinmux_backlight_pins~vaes@480c5000 ti,omap3-aesaesH PPABtxrxprm@48306000 ti,omap3-prmH0`@ clocks+virt_16_8m_ck fixed-clockYvosc_sys_ck@d40 ti,mux-clock @vsys_ck@1270ti,divider-clockpv sys_clkout1@d70ti,gate-clock pdpll3_x2_ckfixed-factor-clock3>dpll3_m2x2_ckfixed-factor-clock3>vdpll4_x2_ckfixed-factor-clock3>corex2_fckfixed-factor-clock3>v!wkup_l4_ickfixed-factor-clock 3>vPcorex2_d3_fckfixed-factor-clock!3>vcorex2_d5_fckfixed-factor-clock!3>vclockdomainscm@48004000 ti,omap3-cmH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clockvBvirt_12m_ck fixed-clockvvirt_13m_ck fixed-clock]@vvirt_19200000_ck fixed-clock$vvirt_26000000_ck fixed-clockvvirt_38_4m_ck fixed-clockIvdpll4_ck@d00ti,omap3-dpll-per-j-type-clock  D 0vdpll4_m2_ck@d48ti,divider-clock? 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Hv/omap_54m_fck@d40 ti,mux-clock/0 @v:cm_96m_d2_fckfixed-factor-clock,3>v1omap_48m_fck@d40 ti,mux-clock10 @v2omap_12m_fckfixed-factor-clock23>vIdpll4_m4_ck@e40ti,divider-clock @v3dpll4_m4x2_mul_ckti,fixed-factor-clock3^lyv4dpll4_m4x2_ck@d00ti,gate-clock4 Hyvdpll4_m5_ck@f40ti,divider-clock?@v5dpll4_m5x2_mul_ckti,fixed-factor-clock5^lyv6dpll4_m5x2_ck@d00ti,hsdiv-gate-clock6 Hyvldpll4_m6_ck@1140ti,divider-clock?@v7dpll4_m6x2_mul_ckfixed-factor-clock73>v8dpll4_m6x2_ck@d00ti,hsdiv-gate-clock8 Hv9emu_per_alwon_ckfixed-factor-clock93>veclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock( pv;clkout2_src_mux_ck@d70ti,composite-mux-clock( ,: pv<clkout2_src_ckti,composite-clock;<v=sys_clkout2@d70ti,divider-clock=@ pmpu_ckfixed-factor-clock>3>v?arm_fck@924ti,divider-clock? $emu_mpu_alwon_ckfixed-factor-clock?3>vfl3_ick@a40ti,divider-clock( @v@l4_ick@a40ti,divider-clock@ @vArm_ick@c40ti,divider-clockA @gpt10_gate_fck@a00ti,composite-gate-clock   vCgpt10_mux_fck@a40ti,composite-mux-clockB  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vwdt2_ick@c10ti,omap3-interface-clockP vwdt1_ick@c10ti,omap3-interface-clockP vgpio1_ick@c10ti,omap3-interface-clockP vomap_32ksync_ick@c10ti,omap3-interface-clockP vgpt12_ick@c10ti,omap3-interface-clockP vgpt1_ick@c10ti,omap3-interface-clockP vper_96m_fckfixed-factor-clock+3>v per_48m_fckfixed-factor-clock23>vQuart3_fck@1000ti,wait-gate-clockQ vgpt2_gate_fck@1000ti,composite-gate-clock vRgpt2_mux_fck@1040ti,composite-mux-clockB @vSgpt2_fckti,composite-clockRSgpt3_gate_fck@1000ti,composite-gate-clock vTgpt3_mux_fck@1040ti,composite-mux-clockB @vUgpt3_fckti,composite-clockTUgpt4_gate_fck@1000ti,composite-gate-clock vVgpt4_mux_fck@1040ti,composite-mux-clockB @vWgpt4_fckti,composite-clockVWgpt5_gate_fck@1000ti,composite-gate-clock vXgpt5_mux_fck@1040ti,composite-mux-clockB @vYgpt5_fckti,composite-clockXYgpt6_gate_fck@1000ti,composite-gate-clock vZgpt6_mux_fck@1040ti,composite-mux-clockB @v[gpt6_fckti,composite-clockZ[gpt7_gate_fck@1000ti,composite-gate-clock v\gpt7_mux_fck@1040ti,composite-mux-clockB @v]gpt7_fckti,composite-clock\]gpt8_gate_fck@1000ti,composite-gate-clock  v^gpt8_mux_fck@1040ti,composite-mux-clockB @v_gpt8_fckti,composite-clock^_gpt9_gate_fck@1000ti,composite-gate-clock  v`gpt9_mux_fck@1040ti,composite-mux-clockB @vagpt9_fckti,composite-clock`aper_32k_alwon_fckfixed-factor-clockB3>vbgpio6_dbck@1000ti,gate-clockbvgpio5_dbck@1000ti,gate-clockbvgpio4_dbck@1000ti,gate-clockbvgpio3_dbck@1000ti,gate-clockbvgpio2_dbck@1000ti,gate-clockb vwdt3_fck@1000ti,wait-gate-clockb vper_l4_ickfixed-factor-clockA3>vcgpio6_ick@1010ti,omap3-interface-clockcvgpio5_ick@1010ti,omap3-interface-clockcvgpio4_ick@1010ti,omap3-interface-clockcvgpio3_ick@1010ti,omap3-interface-clockcvgpio2_ick@1010ti,omap3-interface-clockc vwdt3_ick@1010ti,omap3-interface-clockc vuart3_ick@1010ti,omap3-interface-clockc vuart4_ick@1010ti,omap3-interface-clockcvgpt9_ick@1010ti,omap3-interface-clockc vgpt8_ick@1010ti,omap3-interface-clockc vgpt7_ick@1010ti,omap3-interface-clockcvgpt6_ick@1010ti,omap3-interface-clockcvgpt5_ick@1010ti,omap3-interface-clockcvgpt4_ick@1010ti,omap3-interface-clockcvgpt3_ick@1010ti,omap3-interface-clockcvgpt2_ick@1010ti,omap3-interface-clockcvmcbsp2_ick@1010ti,omap3-interface-clockcvmcbsp3_ick@1010ti,omap3-interface-clockcvmcbsp4_ick@1010ti,omap3-interface-clockcvmcbsp2_gate_fck@1000ti,composite-gate-clockv mcbsp3_gate_fck@1000ti,composite-gate-clockvmcbsp4_gate_fck@1000ti,composite-gate-clockvemu_src_mux_ck@1140 ti,mux-clock def@vgemu_src_ckti,clkdm-gate-clockgvhpclk_fck@1140ti,divider-clockh@pclkx2_fck@1140ti,divider-clockh@atclk_fck@1140ti,divider-clockh@traceclk_src_fck@1140 ti,mux-clock def@vitraceclk_fck@1140ti,divider-clocki @secure_32k_fck fixed-clockvjgpt12_fckfixed-factor-clockj3>wdt1_fckfixed-factor-clockj3>security_l4_ick2fixed-factor-clockA3>vkaes1_ick@a14ti,omap3-interface-clockk rng_ick@a14ti,omap3-interface-clockk sha11_ick@a14ti,omap3-interface-clockk des1_ick@a14ti,omap3-interface-clockk cam_mclk@f00ti,gate-clocklycam_ick@f10!ti,omap3-no-wait-interface-clockAvcsi2_96m_fck@f00ti,gate-clockvsecurity_l3_ickfixed-factor-clock@3>vmpka_ick@a14ti,omap3-interface-clockm icr_ick@a10ti,omap3-interface-clockL des2_ick@a10ti,omap3-interface-clockL mspro_ick@a10ti,omap3-interface-clockL mailboxes_ick@a10ti,omap3-interface-clockL ssi_l4_ickfixed-factor-clockA3>vtsr1_fck@c00ti,wait-gate-clock  vsr2_fck@c00ti,wait-gate-clock  vsr_l4_ickfixed-factor-clockA3>dpll2_fck@40ti,divider-clock(@vndpll2_ck@4ti,omap3-dpll-clock n$@4vodpll2_m2_ck@44ti,divider-clockoDvpiva2_ck@0ti,wait-gate-clockpvmodem_fck@a00ti,omap3-interface-clock  vsad2d_ick@a10ti,omap3-interface-clock@ vmad2d_ick@a18ti,omap3-interface-clock@ vmspro_fck@a00ti,wait-gate-clock ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock! vqssi_ssr_div_fck_3430es2@a40ti,composite-divider-clock! @$vrssi_ssr_fck_3430es2ti,composite-clockqrvsssi_sst_fck_3430es2fixed-factor-clocks3>vhsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clockK vssi_ick_3430es2@a10ti,omap3-ssi-interface-clockt vusim_gate_fck@c00ti,composite-gate-clockG  vsys_d2_ckfixed-factor-clock 3>vvomap_96m_d2_fckfixed-factor-clockG3>vwomap_96m_d4_fckfixed-factor-clockG3>vxomap_96m_d8_fckfixed-factor-clockG3>vyomap_96m_d10_fckfixed-factor-clockG3> vzdpll5_m2_d4_ckfixed-factor-clocku3>v{dpll5_m2_d8_ckfixed-factor-clocku3>v|dpll5_m2_d16_ckfixed-factor-clocku3>v}dpll5_m2_d20_ckfixed-factor-clocku3>v~usim_mux_fck@c40ti,composite-mux-clock( vwxyz{|}~ @vusim_fckti,composite-clockusim_ick@c10ti,omap3-interface-clockP  vdpll5_ck@d04ti,omap3-dpll-clock   $ L 4vdpll5_m2_ck@d50ti,divider-clock Pvusgx_gate_fck@b00ti,composite-gate-clock( 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