JHD(D-Altera SOCFPGA Cyclone V SoC Development Kit?!altr,socfpga-cyclone5-socdkaltr,socfpga-cyclone5altr,socfpgaaliases,/soc/ethernet@ff7020006/soc/ethernet@ff702000@/soc/serial0@ffc02000H/soc/serial1@ffc03000P/soc/timer0@ffc08000W/soc/timer1@ffc09000^/soc/timer2@ffd00000e/soc/timer3@ffd01000cpuslaltr,socfpga-smpcpu@0!arm,cortex-a9zcpucpu@1!arm,cortex-a9zcpupmu@ff111000!arm,cortex-a9-pmu0intc@fffed000!arm,cortex-a9-gicsoc !simple-buszsocamba !simple-buspdma@ffe01000!arm,pl330arm,primecell`hijklmno  & -apb_pclk2base_fpga_region !fpga-region9can@ffc00000 !bosch,d_can0&Bokaycan@ffc01000 !bosch,d_can0& Bdisabledclkmgr@ffd04000 !altr,clk-mgr@clocksosc1I !fixed-clockV}x@ osc2I !fixed-clock f2s_periph_ref_clkI !fixed-clock f2s_sdram_ref_clkI !fixed-clockmain_pll@40I!altr,socfpga-pll-clock& @ mpuclk@48I!altr,socfpga-perip-clk&  f Hmainclk@4cI!altr,socfpga-perip-clk&  f Ldbg_base_clk@50I!altr,socfpga-perip-clk&  f Pmain_qspi_clk@54I!altr,socfpga-perip-clk& Tmain_nand_sdmmc_clk@58I!altr,socfpga-perip-clk& Xcfg_h2f_usr0_clk@5cI!altr,socfpga-perip-clk& \periph_pll@80I!altr,socfpga-pll-clock &  emac0_clk@88I!altr,socfpga-perip-clk& emac1_clk@8cI!altr,socfpga-perip-clk& per_qsi_clk@90I!altr,socfpga-perip-clk& per_nand_mmc_clk@94I!altr,socfpga-perip-clk& per_base_clk@98I!altr,socfpga-perip-clk& h2f_usr1_clk@9cI!altr,socfpga-perip-clk& sdram_pll@c0I!altr,socfpga-pll-clock & ddr_dqs_clk@c8I!altr,socfpga-perip-clk&ddr_2x_dqs_clk@ccI!altr,socfpga-perip-clk& ddr_dq_clk@d0I!altr,socfpga-perip-clk&!h2f_usr2_clk@d4I!altr,socfpga-perip-clk&"mpu_periph_clkI!altr,socfpga-perip-clk&n1mpu_l2_ram_clkI!altr,socfpga-perip-clk&nl4_main_clkI!altr,socfpga-gate-clk&|`l3_main_clkI!altr,socfpga-perip-clk&nl3_mp_clkI!altr,socfpga-gate-clk& fd|`l3_sp_clkI!altr,socfpga-gate-clk& fdl4_mp_clkI!altr,socfpga-gate-clk& fd|`'l4_sp_clkI!altr,socfpga-gate-clk& fd|`(dbg_at_clkI!altr,socfpga-gate-clk& fh|`dbg_clkI!altr,socfpga-gate-clk& fh|`dbg_trace_clkI!altr,socfpga-gate-clk& fl|`dbg_timer_clkI!altr,socfpga-gate-clk&|`cfg_clkI!altr,socfpga-gate-clk&|`h2f_user0_clkI!altr,socfpga-gate-clk&|` emac_0_clkI!altr,socfpga-gate-clk&|%emac_1_clkI!altr,socfpga-gate-clk&|&usb_mp_clkI!altr,socfpga-gate-clk&| f3spi_m_clkI!altr,socfpga-gate-clk&| f0can0_clkI!altr,socfpga-gate-clk&| fcan1_clkI!altr,socfpga-gate-clk&| f gpio_db_clkI!altr,socfpga-gate-clk&| fh2f_user1_clkI!altr,socfpga-gate-clk&|sdmmc_clkI!altr,socfpga-gate-clk & |sdmmc_clk_dividedI!altr,socfpga-gate-clk&|n*nand_x_clkI!altr,socfpga-gate-clk & | -nand_clkI!altr,socfpga-gate-clk & | nqspi_clkI!altr,socfpga-gate-clk & | .ddr_dqs_clk_gateI!altr,socfpga-gate-clk&|ddr_2x_dqs_clk_gateI!altr,socfpga-gate-clk& |ddr_dq_clk_gateI!altr,socfpga-gate-clk&!|h2f_user2_clkI!altr,socfpga-gate-clk&"|fpga_bridge@ff400000!altr,socfpga-lwhps2fpga-bridge@#a&fpga_bridge@ff500000!altr,socfpga-hps2fpga-bridgeP#`&fpgamgr@ff706000!altr,socfpga-fpga-mgrp` ethernet@ff7000000!altr,socfpga-stmmacsnps,dwmac-3.70asnps,dwmac $`p  smacirq&% -stmmaceth#  stmmaceth Bdisabledethernet@ff7020000!altr,socfpga-stmmacsnps,dwmac-3.70asnps,dwmac $`p  xmacirq&& -stmmaceth#! stmmacethBokay$rgmii-:GTan (zgpio@ff708000!snps,dw-apb-gpiop&'Bokaygpio-controller@0!snps,dw-apb-gpio-port gpio@ff709000!snps,dw-apb-gpiop&'Bokaygpio-controller@0!snps,dw-apb-gpio-port +gpio@ff70a000!snps,dw-apb-gpiop&'Bokaygpio-controller@0!snps,dw-apb-gpio-port i2c@ffc04000!snps,designware-i2c@#,&( BokayVeeprom@51 !atmel,24c32Q rtc@68!dallas,ds1339hi2c@ffc05000!snps,designware-i2cP#-&(  Bdisabledi2c@ffc06000!snps,designware-i2c`#.&(  Bdisabledi2c@ffc07000!snps,designware-i2cp#/&(  Bdisabledeccmgr!altr,socfpga-ecc-managerl2-ecc@ffd08140!altr,socfpga-l2-eccЁ@$%ocram-ecc@ffd08144!altr,socfpga-ocram-eccЁD)cache-controller@fffef000!arm,pl310-cache &   %6DSg{l3regs@0xff800000!altr,l3regssyscondwmmc0@ff704000!altr,socfpga-dw-mshcp@  &'*-biuciuBokay  +,,nand@ff900000!altr,socfpga-denali-nand,nand_datadenali_reg 6&- Bdisabledsram@ffff0000 !mmio-sram)spi@ff705000!cdns,qspi-norpP ?O_&.Bokayn25q00@0!n25q00t22partition@qspi-bootFlash 0 Raw Datapartition@qspi-rootfsFlash 0 jffs2 Filesystemrstmgr@ffd05000 !altr,rst-mgrP#snoop-control-unit@fffec000!arm,cortex-a9-scusdr@ffc25000!altr,sdr-ctlsysconP/sdramedac!altr,sdram-edac"/ 'spi@fff00000!snps,dw-apb-ssi 2&0Bokayspidev@0!rohm,dh2228fvtB@spi@fff01000!snps,dw-apb-ssi 2&0 Bdisabledsysmgr@ffd08000!altr,sys-mgrsysconЀ@9Ѐ$timer@fffec600!arm,cortex-a9-twd-timer  &1timer0@ffc08000!snps,dw-apb-timer &(-timertimer1@ffc09000!snps,dw-apb-timer &(-timertimer2@ffd00000!snps,dw-apb-timer & -timertimer3@ffd01000!snps,dw-apb-timer & -timerserial0@ffc02000!snps,dw-apb-uart  IS&(`22etxrxserial1@ffc03000!snps,dw-apb-uart0 IS&(`22etxrxusbphyo!usb-nop-xceivBokay4usb@ffb00000 !snps,dwc2 }&3-otg#"dwc2z4 usb2-phy Bdisabledusb@ffb40000 !snps,dwc2 &3-otg##dwc2z4 usb2-phyBokaywatchdog@ffd02000 !snps,dw-wdt  & Bokaywatchdog@ffd03000 !snps,dw-wdt0 &  Bdisabledchosen earlyprintkserial0:115200n8memory@0zmemory@leds !gpio-ledshps0 hps_led0 +hps1 hps_led1 +hps2 hps_led2 + hps3 hps_led3 + 3-3-v-regulator!regulator-fixed3.3V2Z2Z, #address-cells#size-cellsmodelcompatibleethernet0ethernet1serial0serial1timer0timer1timer2timer3enable-methoddevice_typeregnext-level-cachephandleinterrupt-parentinterruptsinterrupt-affinity#interrupt-cellsinterrupt-controllerranges#dma-cells#dma-channels#dma-requestsclocksclock-namesfpga-mgrstatus#clock-cellsclock-frequencydiv-regfixed-dividerclk-gateclk-phaseresetsaltr,sysmgr-sysconinterrupt-namesmac-addressreset-namessnps,multicast-filter-binssnps,perfect-filter-entriestx-fifo-depthrx-fifo-depthphy-moderxd0-skew-psrxd1-skew-psrxd2-skew-psrxd3-skew-pstxen-skew-pstxc-skew-psrxdv-skew-psrxc-skew-psgpio-controller#gpio-cellssnps,nr-gpiosi2c-sda-falling-time-nsi2c-scl-falling-time-nspagesizeiramcache-unifiedcache-levelarm,tag-latencyarm,data-latencyprefetch-dataprefetch-instrarm,shared-overridearm,double-linefillarm,double-linefill-incrarm,double-linefill-wraparm,prefetch-droparm,prefetch-offsetbroken-cdbus-widthcap-mmc-highspeedcap-sd-highspeedcd-gpiosvmmc-supplyvqmmc-supplyreg-namesdma-maskcdns,fifo-depthcdns,fifo-widthcdns,trigger-addressspi-max-frequencym25p,fast-readcdns,page-sizecdns,block-sizecdns,read-delaycdns,tshsl-nscdns,tsd2d-nscdns,tchsh-nscdns,tslch-nslabel#reset-cellsaltr,modrst-offsetaltr,sdr-sysconnum-cscpu1-start-addrreg-shiftreg-io-widthdmasdma-names#phy-cellsphysphy-namesbootargsstdout-pathregulator-nameregulator-min-microvoltregulator-max-microvolt