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[SPI0_DOUT][SPI0_DIN][SPI0_CS][SPI0_SCLK][UART1_TxD][UART1_RxD][I2C1_SDA][I2C1_SCL]GPIO-HTP93GPIO-G[MDP_VSYNC_S]NC[CSI0_MCLK][CAM_MCLK1][CSI1_MCLK]TP99[I2C2_SDA][I2C2_SCL][CCI_I2C_SDA1][CCI_I2C_SCL1]FLASH_STROBE_ENFLASH_STROBE_TRIGGPIO-KGPIO-DGPIO-IGPIO-JBLSP6_I2C_SDABLSP6_I2C_SCLGPIO-BGPIO30HDMI_CECHDMI_DDC_CLOCKHDMI_DDC_DATAHDMI_HOT_PLUG_DETECTPCIE0_RST_NPCIE0_CLKREQ_NPCIE0_WAKESD_CARD_DET_NTSIF1_SYNCW_DISABLE_N[BLSP9_UART_TX][BLSP9_UART_RX][BLSP2_UART_CTS_N][BLSP2_UART_RFR_N][BLSP3_UART_TX][BLSP3_UART_RX][I2C0_SDA][I2C0_SCL][UART0_TxD][UART0_RxD][UART0_CTS][UART0_RTS][CODEC_INT1_N][CODEC_INT2_N][BLSP7_I2C_SDA][BLSP7_I2C_SCL]MI2S_MCLK[PCM_CLK][PCM_FS][PCM_DO][PCM_DI]GPIO-ETP87[CODEC_RST_N][PCM1_CLK][PCM1_SYNC][PCM1_DIN][PCM1_DOUT]AUDIO_REF_CLKSLIMBUS_CLKSLIMBUS_DATA0SLIMBUS_DATA1NCNCNCNCTP94NCTP95GPIO-ATP88TP89TP90TP91[SD_DAT0][SD_CMD][SD_DAT3][SD_SCLK]TSIF1_CLKTSIF1_ENTSIF1_DATANCTSIF2_CLKTSIF2_ENTSIF2_DATATSIF2_SYNCNCCAM1_STANDBY_NNCNC[LCD1_RESET_N]BOOT_CONFIG1USB_HUB_RESETCAM1_RST_NNCNCNCNCNCNCNCNCPMI8994_BUAPCIE2_RST_NPCIE2_CLKREQ_NPCIE2_WAKESSC_IRQ_0SSC_IRQ_1SSC_IRQ_2NCGPIO121NCSSC_IRQ_6SSC_IRQ_7GPIO-CBOOT_CONFIG5NCNCBOOT_CONFIG7PCIE1_RST_NPCIE1_CLKREQ_NPCIE1_WAKEGPIO-LNCNCBOOT_CONFIG8NCNCGPS_SSBI2GPS_SSBI1NCNCNCBOOT_CONFIG6NCNCNCNCNCg.blsp1_spi0_defaultgpinmux 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modelinterrupt-parent#address-cells#size-cellscompatiblestdout-pathdevice_typeregrangesno-mapphandlesizealloc-rangesqcom,client-idqcom,vmidenable-methodnext-level-cachecache-levelcpupolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresisinterrupts#clock-cellsclock-frequencyclock-output-namespinctrl-namespinctrl-0qcom,dload-modesyscon#hwlock-cellsmemory-regionhwlocksqcom,rpm-msg-rammboxesqcom,glink-channelsvdd_l1-supplyvdd_l2_l26_l28-supplyvdd_l3_l11-supplyvdd_l4_l27_l31-supplyvdd_l5_l7-supplyvdd_l14_l15-supplyvdd_l20_l21-supplyvdd_l25-supplyregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-allow-set-load#qcom,sensors#thermal-sensor-cells#interrupt-cellsinterrupt-controller#redistributor-regionsredistributor-stride#mbox-cells#reset-cells#power-domain-cellsclocksclock-namesstatuslabelpinctrl-1enable-gpiosreg-namesinterrupt-namesbus-widthcd-gpiosvmmc-supplyvqmmc-supplygpio-controller#gpio-cellsgpio-line-namesfunctionpinsdrive-strengthbias-disableoutput-highbias-pull-downbias-pull-upframe-numberqcom,eeqcom,channeloutput-lowpower-sourceqcom,drive-strengthinput-enabledrive-push-pull#phy-cellsvdda-phy-supplyvdda-pll-supplyvdda-phy-max-microampvdda-pll-max-microampvddp-ref-clk-supplyvddp-ref-clk-max-microampvddp-ref-clk-always-onphysphy-namesvcc-supplyvccq-supplyvccq2-supplyvcc-max-microampvccq-max-microampvccq2-max-microamppower-domainsfreq-table-hzlanes-per-directionassigned-clocksassigned-clock-ratesbitsresetsreset-namesvdda-phy-dpdm-supplynvmem-cellsextcondr_modemaximum-speedbus-rangenum-lanesinterrupt-map-maskinterrupt-mapvdda-supplylinux,pci-domainperst-gpiovddpe-3v3-supplyid-gpioregulator-namestartup-delay-usenable-active-highinterrupts-extendedqcom,smem-statesqcom,smem-state-namesqcom,ipcqcom,smd-edgeqcom,remote-pidqcom,smemqcom,local-pidqcom,entry-name#qcom,smem-state-cellsserial0serial1serial2i2c0i2c1i2c2spi0spi1autorepeatlinux,code