7>83(z3 ,OrangePi One Plus.2xunlong,orangepi-one-plusallwinner,sun50i-h6cpus cpu@02arm,cortex-a53=cpuIMpscicpu@12arm,cortex-a53=cpuIMpscicpu@22arm,cortex-a53=cpuIMpscicpu@32arm,cortex-a53=cpuIMpscidisplay-engine#2allwinner,sun50i-h6-display-engine[ odisabledinternal-osc-clkv 2fixed-clock$iosc osc24M_clkv 2fixed-clockn6osc24Mosc32k_clkv 2fixed-clockosc32k psci 2arm,psci-0.2Tsmctimer2arm,armv8-timer0   soc 2simple-bus bus@100000012allwinner,sun50i-h6-de3allwinner,sun50i-a64-de2I@  @clock@02allwinner,sun50i-h6-de3-clkImodbusvmixer@100000 2allwinner,sun50i-h6-de3-mixer-0Ibusmodports port@1Iendpointvideo-codec@1c0e000!2allwinner,sun50i-h6-video-engineI &%6 ahbmodram Ysyscon@3000000G2allwinner,sun50i-h6-system-controlallwinner,sun50i-a64-system-controlI sram@28000 2mmio-sramI  sram-section@072allwinner,sun50i-h6-sram-callwinner,sun50i-a64-sram-cIsram@1a00000 2mmio-sramI    sram-section@082allwinner,sun50i-h6-sram-c1allwinner,sun4i-a10-sram-c1I clock@30010002allwinner,sun50i-h6-ccuI  hoscloscioscvdma-controller@30020002allwinner,sun50i-h6-dmaI  ++5 busmbus"./sid@30060002allwinner,sun50i-h6-sidI`watchdog@30090a002allwinner,sun50i-h6-wdtallwinner,sun6i-a31-wdtI  2 odisabledpinctrl@300b0002allwinner,sun50i-h6-pinctrlI0356; apbhosclosc:JVk rgmii-pinsB|PD0PD1PD2PD3PD4PD5PD7PD8PD9PD10PD11PD12PD13PD19PD20emac(hdmi-pins |PH8PH9PH10hdmimmc0-pins|PF0PF1PF2PF3PF4PF5mmc0 mmc1-pins|PG0PG1PG2PG3PG4PG5mmc1mmc2-pins5|PC1PC4PC5PC6PC7PC8PC9PC10PC11PC12PC13PC14mmc2uart0-ph-pins|PH0PH1uart0interrupt-controller@3021000 2arm,gic-400 I @ `   Vkmmc@402000012allwinner,sun50i-h6-mmcallwinner,sun50i-a64-mmcIC@ahbmmcahb #default ookay   mmc@402100012allwinner,sun50i-h6-mmcallwinner,sun50i-a64-mmcIDAahbmmcahb $default odisabled mmc@402200032allwinner,sun50i-h6-emmcallwinner,sun50i-a64-emmcI EBahbmmcahb %default odisabled serial@50000002snps,dw-apb-uartI Fookaydefaultserial@50004002snps,dw-apb-uartI G odisabledserial@50008002snps,dw-apb-uartI H odisabledserial@5000c002snps,dw-apb-uartI  I odisabledethernet@502000032allwinner,sun50i-h6-emacallwinner,sun50i-a64-emacI macirq! stmmacethT stmmaceth odisabledmdio2snps,dwmac-mdio usb@510000022allwinner,sun50i-h6-musballwinner,sun8i-a33-musbIt5 mcusb&ookay-otgphy@51004002allwinner,sun50i-h6-usb-phyI$15phy_ctrlpmu0pmu3ilusb0_phyusb3_phy,.usb0_resetusb3_resetookay?J \musb@5101000&2allwinner,sun50i-h6-ehcigeneric-ehciI oqh02ookayusb@5101400&2allwinner,sun50i-h6-ohcigeneric-ohciI oh0ookayusb@5311000&2allwinner,sun50i-h6-ehcigeneric-ehciI1 psk14ookayusb@5311400&2allwinner,sun50i-h6-ohcigeneric-ohciI1 pk1ookayhdmi@60000002allwinner,sun50i-h6-dw-hdmiI @0~|{}!iahbisfrtmdscechdcphdcp-bus9> ctrlhdcp hdmi-phydefault odisabledports port@0Iendpointport@1Ihdmi-phy@60100002allwinner,sun50i-h6-hdmi-phyI~|busmod8phy?tcon-top@65100002allwinner,sun50i-h6-tcon-topIQ bustcon-tv0 tcon-top-tv0:rstvports port@0 Iendpoint@0Iport@1 Iendpoint@2Iport@4 Iendpoint@0Iport@5Iendpointlcd-controller@651500082allwinner,sun50i-h6-tcon-tvallwinner,sun8i-r40-tcon-tvIQP B ahbtcon-ch1<lcdports port@0Iendpointport@1 Iendpoint@1Iclock@70100002allwinner,sun50i-h6-r-ccuI hoscloscioscpll-periphvwatchdog@702040002allwinner,sun50i-h6-wdtallwinner,sun6i-a31-wdtI  ginterrupt-controller@702100062allwinner,sun50i-h6-r-intcallwinner,sun6i-a31-r-intcVkI ` pinctrl@70220002allwinner,sun50i-h6-r-pinctrlI io apbhosclosc:JVk!r-i2c-pins|PL0PL1s_i2ci2c@70814002allwinner,sun6i-a31-i2cI kdefaultookay pmic@36 2x-powers,axp805x-powers,axp806I6 Vk~regulatorsaldo12Z+2ZCvcc-plaldo22Z+2Z Cvcc-ac200aldo32Z+2Z Cvcc25-drambldo1w@+w@ Cvcc-bias-pllbldo2w@+w@Cvcc-efuse-pcie-hdmi-iobldo3w@+w@ Cvcc-dcxoiobldo4cldo12Z+2ZCvcc-3v3 cldo22Z+2Z Cvcc-wifi-1cldo32Z+2Z Cvcc-wifi-2dcdca \+zCvdd-cpudcdcc \+zCvdd-gpudcdcd+Cvdd-sysdcdceO+O Cvcc-dramswaliasesR/soc/serial@5000000chosenZserial0:115200n8leds 2gpio-ledspowerforangepi:red:power!lonstatusforangepi:green:status!vcc5v2regulator-fixedCvcc-5vLK@+LK@ interrupt-parent#address-cells#size-cellsmodelcompatibledevice_typeregenable-methodallwinner,pipelinesstatus#clock-cellsclock-frequencyclock-accuracyclock-output-namesphandleinterruptsrangesallwinner,sramclocksclock-namesresets#reset-cellsremote-endpointdma-channelsdma-requests#dma-cellsgpio-controller#gpio-cellsinterrupt-controller#interrupt-cellspinsfunctiondrive-strengthbias-pull-upreset-namespinctrl-namespinctrl-0vmmc-supplycd-gpiosbus-widthreg-shiftreg-io-widthsysconinterrupt-namesphysphy-namesextcondr_modereg-names#phy-cellsusb0_id_det-gpiosusb0_vbus-supplyusb3_vbus-supplyx-powers,self-working-modevina-supplyvinb-supplyvinc-supplyvind-supplyvine-supplyaldoin-supplybldoin-supplycldoin-supplyregulator-always-onregulator-min-microvoltregulator-max-microvoltregulator-nameserial0stdout-pathlabeldefault-state