;8y(3x$rockchip,rk3328-evbrockchip,rk3328 +7Rockchip RK3328 EVBaliases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000i/ethernet@ff540000s/ethernet@ff550000cpus+cpu@0}cpuarm,cortex-a53xpscicpu@1}cpuarm,cortex-a53xpscicpu@2}cpuarm,cortex-a53xpscicpu@3}cpuarm,cortex-a53xpsci l2-cache0cacheopp_table0operating-points-v2opp-408000000Q~#@4opp-600000000#F~#@opp-8160000000,B@#@opp-1008000000<#@opp-1200000000G(#@opp-1296000000M?d #@amba simple-bus+@dmac@ff1f0000arm,pl330arm,primecell@G Rapb_pclk^ arm-pmuarm,cortex-a53-pmu0Gdefgi display-subsystemrockchip,display-subsystem| psciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer0G   xin24m fixed-clockn6xin24m:i2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s G)7Ri2s_clki2s_hclk txrx disabledi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s G*8Ri2s_clki2s_hclk  txrx disabledi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s G+9Ri2s_clki2s_hclk txrx disabledspdif@ff030000rockchip,rk3328-spdif G.: Rmclkhclk txdefault  disabledpdm@ff040000 rockchip,pdm=RRpdm_clkpdm_hclk rxdefaultsleep  disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd+2io-domains"rockchip,rk3328-io-voltage-domain disabledgrf-gpiorockchip,rk3328-grf-gpio power-controller!rockchip,rk3328-power-controller+pd_hevc@6pd_video@5pd_vpu@8reboot-modesyscon-reboot-mode+2RB>RBLRB \RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart G7&Rbaudclkapb_pclk  txrxdefault hu disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart G8'Rbaudclkapb_pclk  txrxdefault hu disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart G9(Rbaudclkapb_pclk  txrxdefaulthuokayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c G$+7 Ri2cpclkdefault disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c G%+8 Ri2cpclkdefaultokayrk805@18rockchip,rk805 Gxin32krk805-clkout2 default!""""##regulatorsDCDC_REG1 vdd_logic 4 5Iregulator-state-mem[sB@DCDC_REG2vdd_arm 4 5Iregulator-state-mem[s~DCDC_REG3vcc_ddr5Iregulator-state-mem[DCDC_REG4vcc_io2Z2Z5I#regulator-state-mem[s2ZLDO_REG1vcc_18w@w@5Iregulator-state-mem[sw@LDO_REG2 vcc18_emmcw@w@5Iregulator-state-mem[sw@LDO_REG3vdd_10B@B@5Iregulator-state-mem[sB@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c G&+9 Ri2cpclkdefault$ disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c G'+: Ri2cpclkdefault% disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi G1+ Rspiclkapb_pclk  txrxdefault&'() disabledwatchdog@ff1a0000 snps,dw-wdt G(pwm@ff1b0000rockchip,rk3328-pwm< Rpwmpclkdefault* disabledpwm@ff1b0010rockchip,rk3328-pwm< Rpwmpclkdefault+ disabledpwm@ff1b0020rockchip,rk3328-pwm < Rpwmpclkdefault, disabledpwm@ff1b0030rockchip,rk3328-pwm0 G2< Rpwmpclkdefault- disabledthermal-zonessoc-thermal.tripstrip-point0ppassivetrip-point1Lpassive/soc-crits criticalcooling-mapsmap0/0  tsadc@ff250000rockchip,rk3328-tsadc% G:$(P$Rtsadcapb_pclkinitdefaultsleep01=0GB Ntsadc-apbZ2g~okay.efuse@ff260000rockchip,rk3328-efuse&P+> Rpclk_efuse id@7cpu-leakage@17logic-leakage@19cpu-version@1a;adc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc( GP%Rsaradcapb_pclkGV Nsaradc-apb disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-4500TGZW]XY[\"gpgpmmupppp0ppmmu0pp1ppmmu1 RbuscoreGfiommu@ff330200rockchip,iommu3 G` h265e_mmu Raclkiface disablediommu@ff340800rockchip,iommu4@ Gb vepu_mmuF Raclkiface disablediommu@ff350800rockchip,iommu5@ G vpu_mmuF Raclkiface disablediommu@ff360480rockchip,iommu 6@6@ GJ rkvdec_mmuB Raclkiface disabledvop@ff370000rockchip,rk3328-vop7> G x;Raclk_vopdclk_vophclk_vopG Naxiahbdclk3 disabledport+ endpoint@049iommu@ff373f00rockchip,iommu7? G vop_mmu; Raclkiface disabled3hdmi@ff3c0000rockchip,rk3328-dw-hdmi<hG#GFRiahbisfrcec5hdmidefault 678Z2 disabledportsportendpoint94codec@ff410000rockchip,rk3328-codecA* RpclkmclkZ2 disabledphy@ff430000rockchip,rk3328-hdmi-phyC GS:yRsysclkrefoclkrefpclk hdmi_phy; cpu-version disabled5clock-controller@ff440000(rockchip,rk3328-crurockchip,crusysconDZ2*x=&'(ABDC"\5H4$7z:::|(n6n6n6n6#FLGрxhxhрxhxhsyscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfdE+usb2-phy@100rockchip,rk3328-usb2phy:Rphyclk usb480m_phy{7<okay<otg-port$G;<=otg-bvalidotg-idlinestateokayMhost-port G> linestateokayNdwmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcP@ G  =!JNRbiuciuciu-driveciu-sampleNYрokaygqdefault=>?@Adwmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcQ@ G  >"KORbiuciuciu-driveciu-sampleNYрokaygBdefault CDEdwmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcR@ G ?#LPRbiuciuciu-driveciu-sampleNYрokaygqdefault FGHethernet@ff540000rockchip,rk3328-gmacT Gmacirq8dWXZYMRstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macGc NstmmacethZ2 disabledethernet@ff550000rockchip,rk3328-gmacUZ2 Gmacirq8TSSUVIRstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphyGbdNstmmacethmac-phyrmiiI disabledJoutpute7Tmdiosnps,dwmac-mdio+phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22VGddefaultKL'Iusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2X GMRotg9otgASb@ qM usb2-phyokayusb@ff5c0000 generic-ehci\ G N< RusbhostutmiNusbokayusb@ff5d0000 generic-ohci] G N< RusbhostutmiNusbokayinterrupt-controller@ff811000 arm,gic-400{@ @ `  G pinctrlrockchip,rk3328-pinctrlZ2+@gpio0@ff210000rockchip,gpio-bank! G3 {\gpio1@ff220000rockchip,gpio-bank" G4 {[gpio2@ff230000rockchip,gpio-bank# G5 { gpio3@ff240000rockchip,gpio-bank$ G6 {pcfg-pull-upQpcfg-pull-downYpcfg-pull-noneOpcfg-pull-none-2maXpcfg-pull-up-2mapcfg-pull-up-4maRpcfg-pull-none-4maUpcfg-pull-down-4mapcfg-pull-none-8maSpcfg-pull-up-8maTpcfg-pull-none-12ma Vpcfg-pull-up-12ma Wpcfg-output-highpcfg-output-lowpcfg-input-highPpcfg-inputi2c0i2c0-xfer OOi2c1i2c1-xfer OOi2c2i2c2-xfer  OO$i2c3i2c3-xfer OO%i2c3-gpio OOhdmi_i2chdmii2c-xfer OO7pdm-0pdmm0-clkO pdmm0-fsyncOpdmm0-sdi0Opdmm0-sdi1Opdmm0-sdi2Opdmm0-sdi3Opdmm0-clk-sleepPpdmm0-sdi0-sleepPpdmm0-sdi1-sleepPpdmm0-sdi2-sleepPpdmm0-sdi3-sleepPpdmm0-fsync-sleepPtsadcotp-gpio O0otp-out O1uart0uart0-xfer  QOuart0-cts Ouart0-rts Ouart0-rts-gpio Ouart1uart1-xfer QOuart1-ctsOuart1-rtsOuart1-rts-gpioOuart2-0uart2m0-xfer QOuart2-1uart2m1-xfer QOspi0-0spi0m0-clkQspi0m0-cs0 Qspi0m0-tx Qspi0m0-rx Qspi0m0-cs1 Qspi0-1spi0m1-clkQspi0m1-cs0Qspi0m1-txQspi0m1-rxQspi0m1-cs1Qspi0-2spi0m2-clkQ&spi0m2-cs0Q)spi0m2-txQ'spi0m2-rxQ(i2s1i2s1-mclkOi2s1-sclkOi2s1-lrckrxOi2s1-lrcktxOi2s1-sdiOi2s1-sdoOi2s1-sdio1Oi2s1-sdio2Oi2s1-sdio3Oi2s1-sleepPPPPPPPPPi2s2-0i2s2m0-mclkOi2s2m0-sclkOi2s2m0-lrckrxOi2s2m0-lrcktxOi2s2m0-sdiOi2s2m0-sdoOi2s2m0-sleep`PPPPPPi2s2-1i2s2m1-mclkOi2s2m1-sclkOi2sm1-lrckrxOi2s2m1-lrcktxOi2s2m1-sdiOi2s2m1-sdoOi2s2m1-sleepPPPPPPspdif-0spdifm0-txOspdif-1spdifm1-txOspdif-2spdifm2-txO sdmmc0-0sdmmc0m0-pwrenRsdmmc0m0-gpioRsdmmc0-1sdmmc0m1-pwrenRsdmmc0m1-gpioR]sdmmc0sdmmc0-clkS=sdmmc0-cmdT>sdmmc0-dectnR?sdmmc0-wrprtRsdmmc0-bus1Tsdmmc0-bus4@TTTT@sdmmc0-gpioRRRRRRRRsdmmc0extsdmmc0ext-clkUsdmmc0ext-cmdRsdmmc0ext-wrprtRsdmmc0ext-dectnRsdmmc0ext-bus1Rsdmmc0ext-bus4@RRRRsdmmc0ext-gpioRRRRRRRRsdmmc1sdmmc1-clk SEsdmmc1-cmd TDsdmmc1-pwrenTsdmmc1-wrprtTsdmmc1-dectnTsdmmc1-bus1Tsdmmc1-bus4@TTTTCsdmmc1-gpio R RRRRRRRRemmcemmc-clkVFemmc-cmdWGemmc-pwrenOemmc-rstnoutOemmc-bus1Wemmc-bus4@WWWWemmc-bus8WWWWWWWWHpwm0pwm0-pinO*pwm1pwm1-pinO+pwm2pwm2-pinO,pwmirpwmir-pinO-gmac-1rgmiim1-pins` S UUSUUU U US SUUSSS SUSSSSrmiim1-pinsXVXXXX X XV V O OOOOOgmac2phyfephyled-speed100Ofephyled-speed10Ofephyled-duplexOfephyled-rxm0Ofephyled-txm0Ofephyled-linkm0Ofephyled-rxm1OKfephyled-txm1Ofephyled-linkm1OLtsadc_pintsadc-int Otsadc-gpio Ohdmi_pinhdmi-cecO6hdmi-hpdY8cif-0dvp-d2d9-m0OOOOO O O OOOOOcif-1dvp-d2d9-m1OOOOOOOOOOOOpmicpmic-int-lQ!sdio-pwrseqwifi-enable-hOZchosen serial2:1500000n8dc-12vregulator-fixeddc_12v5I^sdio-pwrseqmmc-pwrseq-simpledefaultZ [Bsdmmc-regulatorregulator-fixed #\default]vcc_sd2Z2Z(#Avcc-sysregulator-fixedvcc_sys5ILK@LK@(^"vcc-phy-regulatorregulator-fixedvcc_phy5IJ compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1device_typeregclocks#cooling-cellsdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrangesinterruptsclock-names#dma-cellsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesdmasdma-names#sound-dai-cellsstatuspinctrl-namespinctrl-0pinctrl-1gpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommusremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablephy-modephy-handlephy-supplyclock_in_outassigned-clock-ratephy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dma#interrupt-cellsinterrupt-controllerbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathreset-gpiosgpiovin-supply