|8}(d|&firefly,roc-rk3328-ccrockchip,rk3328 +7Firefly roc-rk3328-ccaliases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000i/ethernet@ff540000s/ethernet@ff550000cpus+cpu@0}cpuarm,cortex-a53xpscicpu@1}cpuarm,cortex-a53xpscicpu@2}cpuarm,cortex-a53xpscicpu@3}cpuarm,cortex-a53xpsci l2-cache0cacheopp_table0operating-points-v2opp-408000000Q~#@4opp-600000000#F~#@opp-8160000000,B@#@opp-1008000000<#@opp-1200000000G(#@opp-1296000000M?d #@amba simple-bus+@dmac@ff1f0000arm,pl330arm,primecell@G Rapb_pclk^ arm-pmuarm,cortex-a53-pmu0Gdefgi display-subsystemrockchip,display-subsystem| psciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer0G   xin24m fixed-clockn6xin24m=i2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s G)7Ri2s_clki2s_hclk txrx disabledi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s G*8Ri2s_clki2s_hclk  txrx disabledi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s G+9Ri2s_clki2s_hclk txrx disabledspdif@ff030000rockchip,rk3328-spdif G.: Rmclkhclk txdefault  disabledpdm@ff040000 rockchip,pdm=RRpdm_clkpdm_hclk rxdefaultsleep  disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd+5io-domains"rockchip,rk3328-io-voltage-domainokay %3AOgrf-gpiorockchip,rk3328-grf-gpio\l]power-controller!rockchip,rk3328-power-controllerx+pd_hevc@6pd_video@5pd_vpu@8reboot-modesyscon-reboot-modeRBRBRB RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart G7&Rbaudclkapb_pclk  txrxdefault  disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart G8'Rbaudclkapb_pclk  txrxdefault   disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart G9(Rbaudclkapb_pclk  txrxdefault!okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c G$+7 Ri2cpclkdefault" disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c G%+8 Ri2cpclkdefault#okaypmic@18rockchip,rk805 $Gxin32krk805-clkout2\ldefault%&&'&3&?K`regulatorsDCDC_REG1 Wvdd_logicf 4~ regulator-state-memB@DCDC_REG2Wvdd_armf 4~ regulator-state-mem~DCDC_REG3Wvcc_ddrregulator-state-memDCDC_REG4Wvcc_iof2Z~2Zregulator-state-mem2ZLDO_REG1Wvcc_18fw@~w@regulator-state-memw@LDO_REG2 Wvcc18_emmcfw@~w@regulator-state-memw@LDO_REG3Wvdd_10fB@~B@regulator-state-memB@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c G&+9 Ri2cpclkdefault' disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c G'+: Ri2cpclkdefault( disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi G1+ Rspiclkapb_pclk  txrxdefault)*+, disabledwatchdog@ff1a0000 snps,dw-wdt G(pwm@ff1b0000rockchip,rk3328-pwm< Rpwmpclkdefault- disabledpwm@ff1b0010rockchip,rk3328-pwm< Rpwmpclkdefault. disabledpwm@ff1b0020rockchip,rk3328-pwm < Rpwmpclkdefault/ disabledpwm@ff1b0030rockchip,rk3328-pwm0 G2< Rpwmpclkdefault0 disabledthermal-zonessoc-thermal11tripstrip-point0ApMpassivetrip-point1ALMpassive2soc-critAsM criticalcooling-mapsmap0X20] ltsadc@ff250000rockchip,rk3328-tsadc% G:y$P$Rtsadcapb_pclkinitdefaultsleep343B tsadc-apb5okay1efuse@ff260000rockchip,rk3328-efuse&P+> Rpclk_efuse id@7cpu-leakage@17logic-leakage@19cpu-version@1a >adc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc( GP%Rsaradcapb_pclkV saradc-apb disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-4500TGZW]XY[\" gpgpmmupppp0ppmmu0pp1ppmmu1 Rbuscorefiommu@ff330200rockchip,iommu3 G`  h265e_mmu Raclkiface0 disablediommu@ff340800rockchip,iommu4@ Gb  vepu_mmuF Raclkiface0 disablediommu@ff350800rockchip,iommu5@ G  vpu_mmuF Raclkiface0 disablediommu@ff360480rockchip,iommu 6@6@ GJ  rkvdec_mmuB Raclkiface0 disabledvop@ff370000rockchip,rk3328-vop7> G x;Raclk_vopdclk_vophclk_vop axiahbdclk=6okayport+ endpoint@0D7<iommu@ff373f00rockchip,iommu7? G  vop_mmu; Raclkiface0okay6hdmi@ff3c0000rockchip,rk3328-dw-hdmi<G#GFRiahbisfrcecT8Yhdmidefault 9:;5okayportsportendpointD<7codec@ff410000rockchip,rk3328-codecA* Rpclkmclk5 disabledphy@ff430000rockchip,rk3328-hdmi-phyC GS=yRsysclkrefoclkrefpclk hdmi_phyc> ocpu-versionokay8clock-controller@ff440000(rockchip,rk3328-crurockchip,crusysconD5yx=&'(ABDC"\5H4$z===|n6n6n6n6#FLGрxhxhрxhxhsyscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfdE+usb2-phy@100rockchip,rk3328-usb2phy=Rphyclk usb480m_phyy{?okay?otg-port$G;<= otg-bvalidotg-idlinestateokayNhost-port G>  linestateokayOdwmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcP@ G  =!JNRbiuciuciu-driveciu-sampleрokaydefault@ABC '5DAdwmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcQ@ G  >"KORbiuciuciu-driveciu-sampleр disableddwmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcR@ G ?#LPRbiuciuciu-driveciu-sampleрokayN[jdefault EFG5Aethernet@ff540000rockchip,rk3328-gmacT G macirq8dWXZYMRstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macc stmmaceth5okayydfHHxinputIrgmiidefaultJ $ 'P$ethernet@ff550000rockchip,rk3328-gmacU5 G macirq8TSSUVIRstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphybdstmmacethmac-phyrmiiK disabledmdiosnps,dwmac-mdio+phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22VddefaultLMKusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2X GMRotg"otg*<K@ ZTN Yusb2-phyokayusb@ff5c0000 generic-ehci\ G N? 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G3\lud[gpio1@ff220000rockchip,gpio-bank" G4\lud$gpio2@ff230000rockchip,gpio-bank# G5\ludgpio3@ff240000rockchip,gpio-bank$ G6\ludpcfg-pull-upRpcfg-pull-downZpcfg-pull-nonePpcfg-pull-none-2maYpcfg-pull-up-2mapcfg-pull-up-4maSpcfg-pull-none-4maVpcfg-pull-down-4mapcfg-pull-none-8maTpcfg-pull-up-8maUpcfg-pull-none-12ma Wpcfg-pull-up-12ma Xpcfg-output-highpcfg-output-lowpcfg-input-highQpcfg-inputi2c0i2c0-xfer PP"i2c1i2c1-xfer PP#i2c2i2c2-xfer  PP'i2c3i2c3-xfer PP(i2c3-gpio PPhdmi_i2chdmii2c-xfer PP:pdm-0pdmm0-clkP pdmm0-fsyncPpdmm0-sdi0Ppdmm0-sdi1Ppdmm0-sdi2Ppdmm0-sdi3Ppdmm0-clk-sleepQpdmm0-sdi0-sleepQpdmm0-sdi1-sleepQpdmm0-sdi2-sleepQpdmm0-sdi3-sleepQpdmm0-fsync-sleepQtsadcotp-gpio P3otp-out P4uart0uart0-xfer  RPuart0-cts Puart0-rts Puart0-rts-gpio Puart1uart1-xfer RPuart1-ctsPuart1-rtsP uart1-rts-gpioPuart2-0uart2m0-xfer RPuart2-1uart2m1-xfer RP!spi0-0spi0m0-clkRspi0m0-cs0 Rspi0m0-tx Rspi0m0-rx Rspi0m0-cs1 Rspi0-1spi0m1-clkRspi0m1-cs0Rspi0m1-txRspi0m1-rxRspi0m1-cs1Rspi0-2spi0m2-clkR)spi0m2-cs0R,spi0m2-txR*spi0m2-rxR+i2s1i2s1-mclkPi2s1-sclkPi2s1-lrckrxPi2s1-lrcktxPi2s1-sdiPi2s1-sdoPi2s1-sdio1Pi2s1-sdio2Pi2s1-sdio3Pi2s1-sleepQQQQQQQQQi2s2-0i2s2m0-mclkPi2s2m0-sclkPi2s2m0-lrckrxPi2s2m0-lrcktxPi2s2m0-sdiPi2s2m0-sdoPi2s2m0-sleep`QQQQQQi2s2-1i2s2m1-mclkPi2s2m1-sclkPi2sm1-lrckrxPi2s2m1-lrcktxPi2s2m1-sdiPi2s2m1-sdoPi2s2m1-sleepPQQQQQspdif-0spdifm0-txPspdif-1spdifm1-txPspdif-2spdifm2-txP sdmmc0-0sdmmc0m0-pwrenSsdmmc0m0-gpioSsdmmc0-1sdmmc0m1-pwrenSsdmmc0m1-gpioS\sdmmc0sdmmc0-clkT@sdmmc0-cmdUAsdmmc0-dectnSBsdmmc0-wrprtSsdmmc0-bus1Usdmmc0-bus4@UUUUCsdmmc0-gpioSSSSSSSSsdmmc0extsdmmc0ext-clkVsdmmc0ext-cmdSsdmmc0ext-wrprtSsdmmc0ext-dectnSsdmmc0ext-bus1Ssdmmc0ext-bus4@SSSSsdmmc0ext-gpioSSSSSSSSsdmmc1sdmmc1-clk Tsdmmc1-cmd Usdmmc1-pwrenUsdmmc1-wrprtUsdmmc1-dectnUsdmmc1-bus1Usdmmc1-bus4@UUUUsdmmc1-gpio S SSSSSSSSemmcemmc-clkWEemmc-cmdXFemmc-pwrenPemmc-rstnoutPemmc-bus1Xemmc-bus4@XXXXemmc-bus8XXXXXXXXGpwm0pwm0-pinP-pwm1pwm1-pinP.pwm2pwm2-pinP/pwmirpwmir-pinP0gmac-1rgmiim1-pins` T VVTVVV V VT TVVTTT TVTTTTJrmiim1-pinsYWYYYY Y YW W P PPPPPgmac2phyfephyled-speed100Pfephyled-speed10Pfephyled-duplexPfephyled-rxm0Pfephyled-txm0Pfephyled-linkm0Pfephyled-rxm1PLfephyled-txm1Pfephyled-linkm1PMtsadc_pintsadc-int Ptsadc-gpio Phdmi_pinhdmi-cecP9hdmi-hpdZ;cif-0dvp-d2d9-m0PPPPP P P PPPPPcif-1dvp-d2d9-m1PPPPPPPPPPPPpmicpmic-int-lR%usb2usb20-host-drvP^chosenserial2:1500000n8external-gmac-clock fixed-clocksY@ gmac_clkinHdc-12vregulator-fixedWdc_12vf~_sdmmc-regulatorregulator-fixed [default\Wvcc_sdf2Z~2ZDsdmmcio-regulatorregulator-gpio  ]w@2Z Wvcc_sdiovoltagefw@~2Z&vcc-host1-5v-regulatorregulator-fixed' $default^ Wvcc_host1_5v&vcc-sysregulator-fixedWvcc_sysfLK@~LK@_&vcc-phy-regulatorregulator-fixedWvcc_phyIleds gpio-ledspower:firefly:blue:power @heartbeat  `Von#user:firefly:yellow:user@mmc1  `Voff compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1device_typeregclocks#cooling-cellsdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrangesinterruptsclock-names#dma-cellsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesdmasdma-names#sound-dai-cellsstatuspinctrl-namespinctrl-0pinctrl-1vccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplypmuio-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommusremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplymmc-ddr-1_8vmmc-hs200-1_8vnon-removableclock_in_outphy-supplyphy-modesnps,aalsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ussnps,rxpblsnps,txpbltx_delayrx_delayphy-handlephy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dma#interrupt-cellsinterrupt-controllerbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathvin-supplygpiosstatesregulator-typeenable-active-highlabellinux,default-triggerdefault-state