8~t(]~<pine64,rock64rockchip,rk3328 +7Pine64 Rock64aliases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000i/ethernet@ff540000s/ethernet@ff550000cpus+cpu@0}cpuarm,cortex-a53xpscicpu@1}cpuarm,cortex-a53xpscicpu@2}cpuarm,cortex-a53xpscicpu@3}cpuarm,cortex-a53xpsci l2-cache0cacheopp_table0operating-points-v2opp-408000000Q~#@4opp-600000000#F~#@opp-8160000000,B@#@opp-1008000000<#@opp-1200000000G(#@opp-1296000000M?d #@amba simple-bus+@dmac@ff1f0000arm,pl330arm,primecell@G Rapb_pclk^ arm-pmuarm,cortex-a53-pmu0Gdefgi display-subsystemrockchip,display-subsystem| psciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer0G   xin24m fixed-clockn6xin24m?i2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s G)7Ri2s_clki2s_hclk txrx disabledi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s G*8Ri2s_clki2s_hclk  txrxokayportcendpointi2s >i2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s G+9Ri2s_clki2s_hclk txrx disabledspdif@ff030000rockchip,rk3328-spdif G.: Rmclkhclk txdefault okayportdendpointepdm@ff040000 rockchip,pdm=RRpdm_clkpdm_hclk rxdefaultsleep  disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd+6io-domains"rockchip,rk3328-io-voltage-domainokay,:HVdrgrf-gpiorockchip,rk3328-grf-gpiopower-controller!rockchip,rk3328-power-controller+pd_hevc@6pd_video@5pd_vpu@8reboot-modesyscon-reboot-modeRBRBRB RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart G7&Rbaudclkapb_pclk  txrxdefault   disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart G8'Rbaudclkapb_pclk  txrxdefault   ! disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart G9(Rbaudclkapb_pclk  txrxdefault "okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c G$+7 Ri2cpclkdefault # disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c G%+8 Ri2cpclkdefault $okayrk805@18rockchip,rk805 %Gxin32krk805-clkout2default &$2'>'J'V'bn'bregulatorsDCDC_REG1 zvdd_logic 4 0regulator-state-mem B@DCDC_REG2zvdd_arm 4 0regulator-state-mem ~DCDC_REG3zvcc_ddrregulator-state-memDCDC_REG4zvcc_io2Z2Zregulator-state-mem 2ZLDO_REG1zvcc_18w@w@regulator-state-mem w@LDO_REG2 zvcc18_emmcw@w@regulator-state-mem w@LDO_REG3zvdd_10B@B@regulator-state-mem B@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c G&+9 Ri2cpclkdefault ( disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c G'+: Ri2cpclkdefault ) disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi G1+ Rspiclkapb_pclk  txrxdefault *+,-okayspiflash@0jedec,spi-nor(watchdog@ff1a0000 snps,dw-wdt G(pwm@ff1b0000rockchip,rk3328-pwm< Rpwmpclkdefault .: disabledpwm@ff1b0010rockchip,rk3328-pwm< Rpwmpclkdefault /: disabledpwm@ff1b0020rockchip,rk3328-pwm < Rpwmpclkdefault 0: disabledpwm@ff1b0030rockchip,rk3328-pwm0 G2< Rpwmpclkdefault 1: disabledthermal-zonessoc-thermalE[i{2tripstrip-point0ppassivetrip-point1Lpassive3soc-crits criticalcooling-mapsmap030 tsadc@ff250000rockchip,rk3328-tsadc% G:$P$Rtsadcapb_pclkinitdefaultsleep 454B tsadc-apb6)okay?V2efuse@ff260000rockchip,rk3328-efuse&P+> Rpclk_efuseq id@7cpu-leakage@17logic-leakage@19cpu-version@1a@adc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc( GP%Rsaradcapb_pclkV saradc-apb disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-4500TGZW]XY[\"gpgpmmupppp0ppmmu0pp1ppmmu1 Rbuscorefiommu@ff330200rockchip,iommu3 G` h265e_mmu Raclkiface disablediommu@ff340800rockchip,iommu4@ Gb vepu_mmuF Raclkiface disablediommu@ff350800rockchip,iommu5@ G vpu_mmuF Raclkiface disablediommu@ff360480rockchip,iommu 6@6@ GJ rkvdec_mmuB Raclkiface disabledvop@ff370000rockchip,rk3328-vop7> G x;Raclk_vopdclk_vophclk_vop axiahbdclk7okayport+ endpoint@08=iommu@ff373f00rockchip,iommu7? G vop_mmu; Raclkifaceokay7hdmi@ff3c0000rockchip,rk3328-dw-hdmi<G#GFRiahbisfrcec9hdmidefault  :;<6okayportsportendpoint=8codec@ff410000rockchip,rk3328-codecA* Rpclkmclk6okayport@0endpoint> phy@ff430000rockchip,rk3328-hdmi-phyC GS?yRsysclkrefoclkrefpclk hdmi_phy@ cpu-versionokay9clock-controller@ff440000(rockchip,rk3328-crurockchip,crusysconD6x=&'(ABDC"\5H4$z???|n6n6n6n6#FLGрxhxhрxhxhsyscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfdE+usb2-phy@100rockchip,rk3328-usb2phy?Rphyclk usb480m_phy{AokayAotg-port$G;<=otg-bvalidotg-idlinestateokayPhost-port G> linestateokayQdwmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcP@ G  =!JNRbiuciuciu-driveciu-sample,рokay&0BSdefault BCDE^Fdwmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcQ@ G  >"KORbiuciuciu-driveciu-sample,р disableddwmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcR@ G ?#LPRbiuciuciu-driveciu-sample,рokay&0jydefault  GHI^ethernet@ff540000rockchip,rk3328-gmacT Gmacirq8dWXZYMRstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macc stmmaceth6okaydfJJinputrgmiidefault K L 'P $ethernet@ff550000rockchip,rk3328-gmacU6 Gmacirq8TSSUVIRstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphybdstmmacethmac-phyrmiiM disabledmdiosnps,dwmac-mdio+phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22Vddefault NO(Musb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2X GMRotg:hostBTc@ rP usb2-phyokayusb@ff5c0000 generic-ehci\ G NA RusbhostutmiQusbokayusb@ff5d0000 generic-ohci] G NA RusbhostutmiQusbokayinterrupt-controller@ff811000 arm,gic-400|@ @ `  G pinctrlrockchip,rk3328-pinctrl6+@gpio0@ff210000rockchip,gpio-bank! G3|]gpio1@ff220000rockchip,gpio-bank" G4|Lgpio2@ff230000rockchip,gpio-bank# G5|%gpio3@ff240000rockchip,gpio-bank$ G6|pcfg-pull-upTpcfg-pull-down\pcfg-pull-noneRpcfg-pull-none-2ma[pcfg-pull-up-2mapcfg-pull-up-4maUpcfg-pull-none-4maXpcfg-pull-down-4mapcfg-pull-none-8maVpcfg-pull-up-8maWpcfg-pull-none-12ma Ypcfg-pull-up-12ma Zpcfg-output-highpcfg-output-lowpcfg-input-highSpcfg-inputi2c0i2c0-xfer RR#i2c1i2c1-xfer RR$i2c2i2c2-xfer  RR(i2c3i2c3-xfer RR)i2c3-gpio RRhdmi_i2chdmii2c-xfer RR;pdm-0pdmm0-clkRpdmm0-fsyncRpdmm0-sdi0Rpdmm0-sdi1Rpdmm0-sdi2Rpdmm0-sdi3Rpdmm0-clk-sleepSpdmm0-sdi0-sleepSpdmm0-sdi1-sleepSpdmm0-sdi2-sleepSpdmm0-sdi3-sleepSpdmm0-fsync-sleepStsadcotp-gpio R4otp-out R5uart0uart0-xfer  TRuart0-cts Ruart0-rts Ruart0-rts-gpio Ruart1uart1-xfer TRuart1-ctsR uart1-rtsR!uart1-rts-gpioRuart2-0uart2m0-xfer TRuart2-1uart2m1-xfer TR"spi0-0spi0m0-clkTspi0m0-cs0 Tspi0m0-tx Tspi0m0-rx Tspi0m0-cs1 Tspi0-1spi0m1-clkTspi0m1-cs0Tspi0m1-txTspi0m1-rxTspi0m1-cs1Tspi0-2spi0m2-clkT*spi0m2-cs0T-spi0m2-txT+spi0m2-rxT,i2s1i2s1-mclkRi2s1-sclkRi2s1-lrckrxRi2s1-lrcktxRi2s1-sdiRi2s1-sdoRi2s1-sdio1Ri2s1-sdio2Ri2s1-sdio3Ri2s1-sleepSSSSSSSSSi2s2-0i2s2m0-mclkRi2s2m0-sclkRi2s2m0-lrckrxRi2s2m0-lrcktxRi2s2m0-sdiRi2s2m0-sdoRi2s2m0-sleep`SSSSSSi2s2-1i2s2m1-mclkRi2s2m1-sclkRi2sm1-lrckrxRi2s2m1-lrcktxRi2s2m1-sdiRi2s2m1-sdoRi2s2m1-sleepPSSSSSspdif-0spdifm0-txR spdif-1spdifm1-txRspdif-2spdifm2-txRsdmmc0-0sdmmc0m0-pwrenUsdmmc0m0-gpioUsdmmc0-1sdmmc0m1-pwrenUsdmmc0m1-gpioU^sdmmc0sdmmc0-clkVBsdmmc0-cmdWCsdmmc0-dectnUDsdmmc0-wrprtUsdmmc0-bus1Wsdmmc0-bus4@WWWWEsdmmc0-gpioUUUUUUUUsdmmc0extsdmmc0ext-clkXsdmmc0ext-cmdUsdmmc0ext-wrprtUsdmmc0ext-dectnUsdmmc0ext-bus1Usdmmc0ext-bus4@UUUUsdmmc0ext-gpioUUUUUUUUsdmmc1sdmmc1-clk Vsdmmc1-cmd Wsdmmc1-pwrenWsdmmc1-wrprtWsdmmc1-dectnWsdmmc1-bus1Wsdmmc1-bus4@WWWWsdmmc1-gpio U UUUUUUUUemmcemmc-clkYGemmc-cmdZHemmc-pwrenRemmc-rstnoutRemmc-bus1Zemmc-bus4@ZZZZemmc-bus8ZZZZZZZZIpwm0pwm0-pinR.pwm1pwm1-pinR/pwm2pwm2-pinR0pwmirpwmir-pinR1gmac-1rgmiim1-pins` V XXVXXX X XV VXXVVV VXVVVVKrmiim1-pins[Y[[[[ [ [Y Y R RRRRRgmac2phyfephyled-speed100Rfephyled-speed10Rfephyled-duplexRfephyled-rxm0Rfephyled-txm0Rfephyled-linkm0Rfephyled-rxm1RNfephyled-txm1Rfephyled-linkm1ROtsadc_pintsadc-int Rtsadc-gpio Rhdmi_pinhdmi-cecR:hdmi-hpd\<cif-0dvp-d2d9-m0RRRRR R R RRRRRcif-1dvp-d2d9-m1RRRRRRRRRRRRirir-intRapmicpmic-int-lT&usb2usb20-host-drvR`usb3usb30-host-drvR_chosen serial2:1500000n8external-gmac-clock fixed-clocksY@ gmac_clkinJsdmmc-regulatorregulator-fixed ]default ^zvcc_sd2Z2ZFvcc-host-5v-regulatorregulator-fixed# ]default _ zvcc_host_5v'vcc-host1-5v-regulatorregulator-fixed ]default ` zvcc_host1_5v'vcc-sysregulator-fixedzvcc_sysLK@LK@'ir-receivergpio-ir-receiver 6% adefaultleds gpio-ledspower 6b