H(RTSM_VE_AEMv8A arm,rtsm_ve,aemv8aarm,vexpress"1clk24mhz fixed-clock=Jn6 Zv2m:clk24mhzmrefclk1mhz fixed-clock=JB@Zv2m:refclk1mhzmrefclk32khz fixed-clock=JZv2m:refclk32khzmv2m-3v3regulator-fixedu3V32Z2Zmmccarm,vexpress,config-busoscclk1arm,vexpress-oscjep= Zv2m:oscclk1mresetarm,vexpress-resetmuxfpgaarm,vexpress-muxfpgashutdownarm,vexpress-shutdownrebootarm,vexpress-reboot dvimodearm,vexpress-dvimode bus@8000000 simple-bus"1x  ?2            !!""##$$%%&&''(())**motherboard-bus@rs1arm,vexpress,v2m-p1simple-bus"1flash@0arm,vexpress-flashcfi-flashSWethernet@202000000smsc,lan91c111 Sbiofpga-bus@300000000 simple-bus"1 sysreg@10000arm,vexpress-sysregSm}msysctl@20000arm,sp810arm,primecellS refclktimclkapb_pclk=0Ztimerclken0timerclken1timerclken2timerclken3 maaci@40000arm,pl041arm,primecellSb  apb_pclkmmci@50000arm,pl180arm,primecellSb   mclkapb_pclkkmi@60000arm,pl050arm,primecellSb KMIREFCLKapb_pclkkmi@70000arm,pl050arm,primecellSb KMIREFCLKapb_pclkserial@90000arm,pl011arm,primecellS buartclkapb_pclkserial@a0000arm,pl011arm,primecellS buartclkapb_pclkserial@b0000arm,pl011arm,primecellS buartclkapb_pclkserial@c0000arm,pl011arm,primecellS buartclkapb_pclkwdt@f0000arm,sp805arm,primecellSbwdogclkapb_pclktimer@110000arm,sp804arm,primecellSbtimclken1timclken2apb_pclktimer@120000arm,sp804arm,primecellSbtimclken1timclken2apb_pclkvirtio-block@130000 virtio,mmioSb*rtc@170000arm,pl031arm,primecellSb apb_pclkclcd@1f0000arm,pl111arm,primecellS combinedbclcdclkapb_pclk portendpoint  m chosenaliases?7/bus@8000000/motherboard-bus/iofpga-bus@300000000/serial@90000??/bus@8000000/motherboard-bus/iofpga-bus@300000000/serial@a0000?G/bus@8000000/motherboard-bus/iofpga-bus@300000000/serial@b0000?O/bus@8000000/motherboard-bus/iofpga-bus@300000000/serial@c0000cpus"1cpu@0Wcpu arm,armv8S cspin-tableq cpu@1Wcpu arm,armv8S cspin-tableq cpu@2Wcpu arm,armv8S cspin-tableq cpu@3Wcpu arm,armv8S cspin-tableq l2-cache0cachem memory@80000000Wmemory Sreserved-memory"1vram@18000000shared-dma-poolSm interrupt-controller@2c001000arm,gic-400arm,cortex-a15-gic"@S,, ,@ ,`  b mtimerarm,armv8-timer0b   Jpmuarm,armv8-pmuv30b<=>?panelarm,rtsm-displayportendpoint m  modelcompatibleinterrupt-parent#address-cells#size-cells#clock-cellsclock-frequencyclock-output-namesphandleregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onarm,vexpress,config-bridgearm,vexpress-sysreg,funcfreq-rangeranges#interrupt-cellsinterrupt-map-maskinterrupt-maparm,v2m-memory-mapregbank-widthinterruptsgpio-controller#gpio-cellsclocksclock-namesassigned-clocksassigned-clock-parentscd-gpioswp-gpiosmax-frequencyvmmc-supplyinterrupt-namesmemory-regionremote-endpointarm,pl11x,tft-r0g0b0-padsserial0serial1serial2serial3device_typeenable-methodcpu-release-addrnext-level-cacheno-mapinterrupt-controller