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#address-cells#size-cellsinterrupt-parentmodelcompatibleregcache-unifiedcache-levelarm,data-latencyarm,tag-latencyarm,filter-rangesprefetch-dataprefetch-instrarm,shared-overridephandle#clock-cells#reset-cellsclocksclock-namesinterruptsstatuspinctrl-0pinctrl-namesuart-has-rtscts#pwm-cells#io-channel-cellsamlogic,hhi-sysctrlnvmem-cellsnvmem-cell-namesvref-supply#phy-cellsresetsbus-widthno-sdiocap-mmc-highspeedcap-sd-highspeeddisable-wpcd-gpiosvmmc-supplyinterrupt-controller#interrupt-cellsamlogic,channel-interruptsreg-namesgpio-controller#gpio-cellsgpio-rangesgroupsfunctionbias-disablesystem-power-controllerregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-boot-onregulator-always-onphysphy-namesdr_modeinterrupt-namesreset-namesphy-handlephy-modeamlogic,tx-delay-nsreset-assert-usreset-deassert-usreset-gpiosdevice_typenext-level-cacheenable-methodoperating-points-v2cpu-supplyopp-sharedopp-hzopp-microvoltturbo-modeinterrupt-affinityno-mapmali-supplyethernet0i2c0serial0serial1mmc0stdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltlabellinux,codepress-threshold-microvolt