#8<(+compulab,omap3-cm-t3517ti,am3517ti,omap3 +7CompuLab CM-T3517chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000d/ocp@68000000/serial@4809e000l/ocp@68000000/can@5c050000cpus+cpu@0arm,cortex-a8pcpu|cpupmu@54000000arm,cortex-a8-pmu|Tdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2iva disableddsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bus|h +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus| + pinmux@30 ti,omap3-padconfpinctrl-single|08+pinmux_uart3_pins4npHpinmux_mmc1_pins04Hpinmux_green_led_pins4Hpinmux_dss_dpi_pins_common4Hpinmux_dss_dpi_pins_cm_t35x04Hpinmux_ads7846_pins4Hpinmux_mcspi1_pins 4Hpinmux_i2c1_pins4Hpinmux_mcbsp2_pins 4 Hpinmux_hsusb1_phy_reset_pins4HHpinmux_hsusb2_phy_reset_pins4JHpinmux_otg_drv_vbus4Hpinmux_mmc2_pins04(*,.02Hpinmux_wl12xx_core_pins4FHpinmux_usb_hub_pins4Tscm_conf@270sysconsimple-bus|p0+ p0Hpbias_regulator@2b0ti,pbias-omap3ti,pbias-omap|Ppbias_mmc_omap2430Wpbias_mmc_omap2430fw@~-Hclocks+mcbsp5_mux_fck@68ti,composite-mux-clock|hHmcbsp5_fckti,composite-clockHmcbsp1_mux_fck@4ti,composite-mux-clock|H mcbsp1_fckti,composite-clock Hmcbsp2_mux_fck@4ti,composite-mux-clock |H mcbsp2_fckti,composite-clock Hmcbsp3_mux_fck@68ti,composite-mux-clock |hHmcbsp3_fckti,composite-clock Hmcbsp4_mux_fck@68ti,composite-mux-clock |hHmcbsp4_fckti,composite-clockHemac_ick@32cti,am35xx-gate-clock|,Hxemac_fck@32cti,gate-clock|, Hvpfe_ick@32cti,am35xx-gate-clock|,Hyvpfe_fck@32cti,gate-clock|, hsotgusb_ick_am35xx@32cti,am35xx-gate-clock|,Hzhsotgusb_fck_am35xx@32cti,gate-clock|,H{hecc_ck@32cti,am35xx-gate-clock|,H|clockdomainspinmux@a00 ti,omap3-padconfpinctrl-single| \+pinmux_wl12xx_wkup_pins4Haes@480c5000 ti,omap3-aesaes|H PPABtxrxprm@48306000 ti,omap3-prm|H0`@ clocks+virt_16_8m_ck fixed-clockYHosc_sys_ck@d40 ti,mux-clock| @Hsys_ck@1270ti,divider-clock|pHsys_clkout1@d70ti,gate-clock| pdpll3_x2_ckfixed-factor-clockdpll3_m2x2_ckfixed-factor-clockH dpll4_x2_ckfixed-factor-clockcorex2_fckfixed-factor-clock H!wkup_l4_ickfixed-factor-clockHPcorex2_d3_fckfixed-factor-clock!Hqcorex2_d5_fckfixed-factor-clock!Hrclockdomainscm@48004000 ti,omap3-cm|H@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clockHBvirt_12m_ck fixed-clockHvirt_13m_ck fixed-clock]@Hvirt_19200000_ck fixed-clock$Hvirt_26000000_ck fixed-clockHvirt_38_4m_ck fixed-clockIHdpll4_ck@d00ti,omap3-dpll-per-clock| D 0Hdpll4_m2_ck@d48ti,divider-clock?| HH"dpll4_m2x2_mul_ckfixed-factor-clock"H#dpll4_m2x2_ck@d00ti,gate-clock#| H$omap_96m_alwon_fckfixed-factor-clock$H+dpll3_ck@d00ti,omap3-dpll-core-clock| @ 0Hdpll3_m3_ck@1140ti,divider-clock|@H%dpll3_m3x2_mul_ckfixed-factor-clock%H&dpll3_m3x2_ck@d00ti,gate-clock& | H'emu_core_alwon_ckfixed-factor-clock'Hdsys_altclk fixed-clockH0mcbsp_clks fixed-clockHdpll3_m2_ck@d40ti,divider-clock| @Hcore_ckfixed-factor-clockH(dpll1_fck@940ti,divider-clock(| @H)dpll1_ck@904ti,omap3-dpll-clock)|  $ @ 4Hdpll1_x2_ckfixed-factor-clockH*dpll1_x2m2_ck@944ti,divider-clock*| DH>cm_96m_fckfixed-factor-clock+H,omap_96m_fck@d40 ti,mux-clock,| @HGdpll4_m3_ck@e40ti,divider-clock |@H-dpll4_m3x2_mul_ckfixed-factor-clock-H.dpll4_m3x2_ck@d00ti,gate-clock.| H/omap_54m_fck@d40 ti,mux-clock/0| @H:cm_96m_d2_fckfixed-factor-clock,H1omap_48m_fck@d40 ti,mux-clock10| @H2omap_12m_fckfixed-factor-clock2HIdpll4_m4_ck@e40ti,divider-clock |@H3dpll4_m4x2_mul_ckti,fixed-factor-clock3*7H4dpll4_m4x2_ck@d00ti,gate-clock4| 7Hvdpll4_m5_ck@f40ti,divider-clock?|@H5dpll4_m5x2_mul_ckti,fixed-factor-clock5*7H6dpll4_m5x2_ck@d00ti,gate-clock6| 7dpll4_m6_ck@1140ti,divider-clock?|@H7dpll4_m6x2_mul_ckfixed-factor-clock7H8dpll4_m6x2_ck@d00ti,gate-clock8| H9emu_per_alwon_ckfixed-factor-clock9Heclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock(| pH;clkout2_src_mux_ck@d70ti,composite-mux-clock(,:| pH<clkout2_src_ckti,composite-clock;<H=sys_clkout2@d70ti,divider-clock=@| pJmpu_ckfixed-factor-clock>H?arm_fck@924ti,divider-clock?| $emu_mpu_alwon_ckfixed-factor-clock?Hfl3_ick@a40ti,divider-clock(| @H@l4_ick@a40ti,divider-clock@| @HArm_ick@c40ti,divider-clockA| @gpt10_gate_fck@a00ti,composite-gate-clock | HCgpt10_mux_fck@a40ti,composite-mux-clockB| @HDgpt10_fckti,composite-clockCDgpt11_gate_fck@a00ti,composite-gate-clock | HEgpt11_mux_fck@a40ti,composite-mux-clockB| @HFgpt11_fckti,composite-clockEFcore_96m_fckfixed-factor-clockGHmmchs2_fck@a00ti,wait-gate-clock| Hmmchs1_fck@a00ti,wait-gate-clock| Hi2c3_fck@a00ti,wait-gate-clock| Hi2c2_fck@a00ti,wait-gate-clock| Hi2c1_fck@a00ti,wait-gate-clock| Hmcbsp5_gate_fck@a00ti,composite-gate-clock | Hmcbsp1_gate_fck@a00ti,composite-gate-clock | Hcore_48m_fckfixed-factor-clock2HHmcspi4_fck@a00ti,wait-gate-clockH| Hmcspi3_fck@a00ti,wait-gate-clockH| Hmcspi2_fck@a00ti,wait-gate-clockH| Hmcspi1_fck@a00ti,wait-gate-clockH| Huart2_fck@a00ti,wait-gate-clockH| Huart1_fck@a00ti,wait-gate-clockH|  Hcore_12m_fckfixed-factor-clockIHJhdq_fck@a00ti,wait-gate-clockJ| Hcore_l3_ickfixed-factor-clock@HKsdrc_ick@a10ti,wait-gate-clockK| Hwgpmc_fckfixed-factor-clockKcore_l4_ickfixed-factor-clockAHLmmchs2_ick@a10ti,omap3-interface-clockL| Hmmchs1_ick@a10ti,omap3-interface-clockL| Hhdq_ick@a10ti,omap3-interface-clockL| Hmcspi4_ick@a10ti,omap3-interface-clockL| Hmcspi3_ick@a10ti,omap3-interface-clockL| Hmcspi2_ick@a10ti,omap3-interface-clockL| Hmcspi1_ick@a10ti,omap3-interface-clockL| Hi2c3_ick@a10ti,omap3-interface-clockL| Hi2c2_ick@a10ti,omap3-interface-clockL| Hi2c1_ick@a10ti,omap3-interface-clockL| Huart2_ick@a10ti,omap3-interface-clockL| Huart1_ick@a10ti,omap3-interface-clockL|  Hgpt11_ick@a10ti,omap3-interface-clockL|  Hgpt10_ick@a10ti,omap3-interface-clockL|  Hmcbsp5_ick@a10ti,omap3-interface-clockL|  Hmcbsp1_ick@a10ti,omap3-interface-clockL|  Homapctrl_ick@a10ti,omap3-interface-clockL| Hdss_tv_fck@e00ti,gate-clock:|Hdss_96m_fck@e00ti,gate-clockG|Hdss2_alwon_fck@e00ti,gate-clock|Hdummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock| HMgpt1_mux_fck@c40ti,composite-mux-clockB| @HNgpt1_fckti,composite-clockMNaes2_ick@a10ti,omap3-interface-clockL| Hwkup_32k_fckfixed-factor-clockBHOgpio1_dbck@c00ti,gate-clockO| Hsha12_ick@a10ti,omap3-interface-clockL| Hwdt2_fck@c00ti,wait-gate-clockO| Hwdt2_ick@c10ti,omap3-interface-clockP| Hwdt1_ick@c10ti,omap3-interface-clockP| Hgpio1_ick@c10ti,omap3-interface-clockP| Homap_32ksync_ick@c10ti,omap3-interface-clockP| Hgpt12_ick@c10ti,omap3-interface-clockP| Hgpt1_ick@c10ti,omap3-interface-clockP| Hper_96m_fckfixed-factor-clock+H per_48m_fckfixed-factor-clock2HQuart3_fck@1000ti,wait-gate-clockQ| H}gpt2_gate_fck@1000ti,composite-gate-clock|HRgpt2_mux_fck@1040ti,composite-mux-clockB|@HSgpt2_fckti,composite-clockRSgpt3_gate_fck@1000ti,composite-gate-clock|HTgpt3_mux_fck@1040ti,composite-mux-clockB|@HUgpt3_fckti,composite-clockTUgpt4_gate_fck@1000ti,composite-gate-clock|HVgpt4_mux_fck@1040ti,composite-mux-clockB|@HWgpt4_fckti,composite-clockVWgpt5_gate_fck@1000ti,composite-gate-clock|HXgpt5_mux_fck@1040ti,composite-mux-clockB|@HYgpt5_fckti,composite-clockXYgpt6_gate_fck@1000ti,composite-gate-clock|HZgpt6_mux_fck@1040ti,composite-mux-clockB|@H[gpt6_fckti,composite-clockZ[gpt7_gate_fck@1000ti,composite-gate-clock|H\gpt7_mux_fck@1040ti,composite-mux-clockB|@H]gpt7_fckti,composite-clock\]gpt8_gate_fck@1000ti,composite-gate-clock |H^gpt8_mux_fck@1040ti,composite-mux-clockB|@H_gpt8_fckti,composite-clock^_gpt9_gate_fck@1000ti,composite-gate-clock |H`gpt9_mux_fck@1040ti,composite-mux-clockB|@Hagpt9_fckti,composite-clock`aper_32k_alwon_fckfixed-factor-clockBHbgpio6_dbck@1000ti,gate-clockb|H~gpio5_dbck@1000ti,gate-clockb|Hgpio4_dbck@1000ti,gate-clockb|Hgpio3_dbck@1000ti,gate-clockb|Hgpio2_dbck@1000ti,gate-clockb| Hwdt3_fck@1000ti,wait-gate-clockb| Hper_l4_ickfixed-factor-clockAHcgpio6_ick@1010ti,omap3-interface-clockc|Hgpio5_ick@1010ti,omap3-interface-clockc|Hgpio4_ick@1010ti,omap3-interface-clockc|Hgpio3_ick@1010ti,omap3-interface-clockc|Hgpio2_ick@1010ti,omap3-interface-clockc| Hwdt3_ick@1010ti,omap3-interface-clockc| Huart3_ick@1010ti,omap3-interface-clockc| Huart4_ick@1010ti,omap3-interface-clockc|Hgpt9_ick@1010ti,omap3-interface-clockc| Hgpt8_ick@1010ti,omap3-interface-clockc| Hgpt7_ick@1010ti,omap3-interface-clockc|Hgpt6_ick@1010ti,omap3-interface-clockc|Hgpt5_ick@1010ti,omap3-interface-clockc|Hgpt4_ick@1010ti,omap3-interface-clockc|Hgpt3_ick@1010ti,omap3-interface-clockc|Hgpt2_ick@1010ti,omap3-interface-clockc|Hmcbsp2_ick@1010ti,omap3-interface-clockc|Hmcbsp3_ick@1010ti,omap3-interface-clockc|Hmcbsp4_ick@1010ti,omap3-interface-clockc|Hmcbsp2_gate_fck@1000ti,composite-gate-clock|H mcbsp3_gate_fck@1000ti,composite-gate-clock|H mcbsp4_gate_fck@1000ti,composite-gate-clock|Hemu_src_mux_ck@1140 ti,mux-clockdef|@Hgemu_src_ckti,clkdm-gate-clockgHhpclk_fck@1140ti,divider-clockh|@pclkx2_fck@1140ti,divider-clockh|@atclk_fck@1140ti,divider-clockh|@traceclk_src_fck@1140 ti,mux-clockdef|@Hitraceclk_fck@1140ti,divider-clocki |@secure_32k_fck fixed-clockHjgpt12_fckfixed-factor-clockjwdt1_fckfixed-factor-clockjipss_ick@a10ti,am35xx-interface-clockK| Hrmii_ck fixed-clockHpclk_ck fixed-clockHuart4_ick_am35xx@a10ti,omap3-interface-clockL| uart4_fck_am35xx@a00ti,wait-gate-clockH| dpll5_ck@d04ti,omap3-dpll-clock|  $ L 4`rHkdpll5_m2_ck@d50ti,divider-clockk| PHusgx_gate_fck@b00ti,composite-gate-clock(| Hscore_d3_ckfixed-factor-clock(Hlcore_d4_ckfixed-factor-clock(Hmcore_d6_ckfixed-factor-clock(Hnomap_192m_alwon_fckfixed-factor-clock$Hocore_d2_ckfixed-factor-clock(Hpsgx_mux_fck@b40ti,composite-mux-clock lmn,opqr| @Htsgx_fckti,composite-clockstHsgx_ick@b10ti,wait-gate-clock@| Hcpefuse_fck@a08ti,gate-clock| Hts_fck@a08ti,gate-clockB| Husbtll_fck@a08ti,wait-gate-clocku| Husbtll_ick@a18ti,omap3-interface-clockL| Hmmchs3_ick@a10ti,omap3-interface-clockL| Hmmchs3_fck@a00ti,wait-gate-clock| Hdss1_alwon_fck_3430es2@e00ti,dss-gate-clockv|7Hdss_ick_3430es2@e10ti,omap3-dss-interface-clockA|Husbhost_120m_fck@1400ti,gate-clocku|Husbhost_48m_fck@1400ti,dss-gate-clock2|Husbhost_ick@1410ti,omap3-dss-interface-clockA|Hclockdomainscore_l3_clkdmti,clockdomainwxyz{|dpll3_clkdmti,clockdomaindpll1_clkdmti,clockdomainper_clkdmti,clockdomainh}~emu_clkdmti,clockdomainhdpll4_clkdmti,clockdomainwkup_clkdmti,clockdomain dss_clkdmti,clockdomaincore_l4_clkdmti,clockdomaindpll5_clkdmti,clockdomainksgx_clkdmti,clockdomainusbhost_clkdmti,clockdomain counter@48320000ti,omap-counter32k|H2  counter_32kinterrupt-controller@48200000ti,omap3-intc|H Hdma-controller@48056000"ti,omap3630-sdmati,omap3430-sdma|H` z `dmaHgpio@48310000ti,omap3-gpio|H1gpio1Hgpio@49050000ti,omap3-gpio|Igpio2Hgpio@49052000ti,omap3-gpio|I gpio3gpio@49054000ti,omap3-gpio|I@ gpio4gpio@49056000ti,omap3-gpio|I`!gpio5Hgpio@49058000ti,omap3-gpio|I"gpio6Hserial@4806a000ti,omap3-uart|H H12txrxuart1lserial@4806c000ti,omap3-uart|HI34txrxuart2lserial@49020000ti,omap3-uart|IJ56txrxuart3ldefaulti2c@48070000 ti,omap3-i2c|H8txrx+i2c1defaultat24@50 atmel,24c02|Pi2c@48072000 ti,omap3-i2c|H 9txrx+i2c2i2c@48060000 ti,omap3-i2c|H=txrx+i2c3mailbox@48094000ti,omap3-mailboxmailbox|H @  disableddsp 2 =spi@48098000ti,omap2-mcspi|H A+mcspi1H@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3defaultads7846@0default ti,ads7846V|a`  s spi@4809a000ti,omap2-mcspi|H B+mcspi2H +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspi|H [+mcspi3H tx0rx0tx1rx1spi@480ba000ti,omap2-mcspi|H 0+mcspi4HFGtx0rx01w@480b2000 ti,omap3-1w|H :hdq1wmmc@4809c000ti,omap3-hsmmc|H Smmc1=>txrxdefault&mmc@480b4000ti,omap3-hsmmc|H @Vmmc2/0txrxdefault&2?M+wlcore@2 ti,wl1271| `Immc@480ad000ti,omap3-hsmmc|H ^mmc3MNtxrx disabledmmu@480bd400tti,omap2-iommu|H mmu_isp disabledmmu@5d000000tti,omap2-iommu|]mmu_iva disabledwdt@48314000 ti,omap3-wdt|H1@ wd_timer2mcbsp@48074000ti,omap3-mcbsp|H@mpu ;< commontxrxmcbsp1 txrxfck disabledmcbsp@49022000ti,omap3-mcbsp|I I mpusidetone>?commontxrxsidetonemcbsp2mcbsp2_sidetone!"txrxfckickokdefaultmcbsp@49024000ti,omap3-mcbsp|I@I mpusidetoneYZcommontxrxsidetonemcbsp3mcbsp3_sidetonetxrxfckick disabledmcbsp@49026000ti,omap3-mcbsp|I`mpu 67 commontxrxmcbsp4txrxfck disabledmcbsp@48096000ti,omap3-mcbsp|H `mpu QR commontxrxmcbsp5txrxfck disabledsham@480c3000ti,omap3-shamsham|H 0d1Erxtimer@48318000ti,omap3430-timer|H1%timer1timer@49032000ti,omap3430-timer|I &timer2timer@49034000ti,omap3430-timer|I@'timer3timer@49036000ti,omap3430-timer|I`(timer4timer@49038000ti,omap3430-timer|I)timer5timer@4903a000ti,omap3430-timer|I*timer6timer@4903c000ti,omap3430-timer|I+timer7timer@4903e000ti,omap3430-timer|I,timer8timer@49040000ti,omap3430-timer|I-timer9timer@48086000ti,omap3430-timer|H`.timer10timer@48088000ti,omap3430-timer|H/timer11timer@48304000ti,omap3430-timer|H0@_timer12usbhstll@48062000 ti,usbhs-tll|H N usb_tll_hsusbhshost@48064000ti,usbhs-host|H@ usb_host_hs+ ehci-phy ehci-phyohci@48064400ti,ohci-omap3|HDLehci@48064800 ti,ehci-omap|HHM2gpmc@6e000000ti,omap3430-gpmcgpmc|nrxtx7C+0Hnand@0,0ti,omap2-nand | UdvswxxxxZ Z'AHP<jx{xZ+partition@0xloader|partition@80000uboot|partition@260000uboot environment|&partition@2a0000linux|*@partition@6a0000rootfs|jusb_otg_hs@480ab000ti,omap3-musb|H \]mcdma usb_otg_hs  disableddss@48050000 ti,omap3-dss|Hok dss_corefck+defaultdispc@48050400ti,omap3-dispc|H dss_dispcfckencoder@4804fc00 ti,omap3-dsi|HH@H protophypll disabled dss_dsi1 fcksys_clkencoder@48050800ti,omap3-rfbi|H disabled dss_rfbifckickencoder@48050c00ti,omap3-venc|H ok dss_vencfckportendpointHssi-controller@48058000 ti,omap3-ssissi disabled|HHsysgddGgdd_mpu+ssi-port@4805a000ti,omap3-ssi-port|HHtxrxCDssi-port@4805b000ti,omap3-ssi-port|HHtxrxEFam35x_otg_hs@5c040000ti,omap3-musb am35x_otg_hsokay|\Gmcdefaultethernet@5c000000ti,am3517-emac davinci_emacokay|\CDEFP.I buxickethernet@5c030000ti,davinci_mdio davinci_mdiookay|\B@+fckserial@4809e000ti,omap3-uartuart4 disabled|H T76txrxlpinmux@480025d8 ti,omap3-padconfpinctrl-single|H%$+can@5c050000ti,am3517-hecc disabled|\\0\ hecchecc-rammbx|target-module@50000000ti,sysc-omap2ti,sysc|Prevfckick+ P@memory@80000000pmemory|leds gpio-ledsdefaultledb cm-t3x:green  heartbeathsusb1_power_regregulator-fixed Whsusb1_vbusf2Z~2ZpHhsusb2_power_regregulator-fixed Whsusb2_vbusf2Z~2ZpHhsusb1_phyusb-nop-xceivVdefault Hhsusb2_phyusb-nop-xceivVdefault Hads7846-regregulator-fixed Wads7846-regf2Z~2ZHsvideo-connectorsvideo-connectortvportendpointHregulator-vmmcregulator-fixedWvmmcf2Z~2ZHwl12xx_vmmc2regulator-fixedWvw1271defaultfw@~w@ {N Hwl12xx_vaux2regulator-fixedWvwl1271_vaux2fw@~w@H compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2serial3candevice_typeregclocksclock-namesclock-latencyinterruptsti,hwmodsstatusranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinsphandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lock#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0pagesize#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csvcc-supplyspi-max-frequencypendown-gpioti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,debounce-maxti,debounce-tolti,debounce-repwakeup-sourceti,dual-voltpbias-supplybus-widthvmmc-supplyvqmmc-supplynon-removablecap-power-off-cardref-clock-frequency#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-size#sound-dai-cellsti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport1-modeport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,page-burst-access-nsgpmc,access-nsgpmc,cycle2cycle-delay-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelmultipointnum-epsram-bitsremote-endpointti,channelsti,davinci-ctrl-reg-offsetti,davinci-ctrl-mod-reg-offsetti,davinci-ctrl-ram-offsetti,davinci-ctrl-ram-sizeti,davinci-rmii-enlocal-mac-addressbus_freqgpioslinux,default-triggerstartup-delay-us#phy-cellsreset-gpiosenable-active-high