u8(Iheadacoustics,omap3-ha-lcdtechnexion,omap3-tao3530ti,omap34xxti,omap3 +77TI OMAP3 HEAD acoustics LCD-baseboard with TAO3530 SOMchosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000 d/displaycpus+cpu@0arm,cortex-a8mcpuy}cpu(HАg8 Odp` 'ppmu@54000000arm,cortex-a8-pmuyTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busyh +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-busy + pinmux@30 ti,omap3-padconfpinctrl-singley08+ *Gdefault U pinmux_hsusbb2_pins`_          spinmux_mmc1_pinsP_ "$&spinmux_mmc2_pins0_(*,.02spinmux_wlan_gpio_^pinmux_uart3_pins_nApspinmux_i2c3_pins_spinmux_mcspi1_pins _spinmux_mcspi3_pins _spinmux_mcbsp3_pins _<>@Bspinmux_twl4030_pins_Aspinmux_sound2_pins_npinmux_led_blue_pins_spinmux_led_green_pins_s pinmux_led_red_pins_s pinmux_poweroff_pins_spinmux_powerdown_input_pins_sfpga_boot0_pins _sfpga_boot1_pins _rtvxspinmux_touchscreen_irq_pins_4pinmux_touchscreen_wake_pins_s pinmux_dss_dpi_pins_spinmux_lte430_pins_8spinmux_backlight_pins_:sscm_conf@270sysconsimple-busyp0+ p0s pbias_regulator@2b0ti,pbias-omap3ti,pbias-omapy{ pbias_mmc_omap2430pbias_mmc_omap2430w@-sclocks+mcbsp5_mux_fck@68ti,composite-mux-clock} yhsmcbsp5_fckti,composite-clock}smcbsp1_mux_fck@4ti,composite-mux-clock} ysmcbsp1_fckti,composite-clock}smcbsp2_mux_fck@4ti,composite-mux-clock}ysmcbsp2_fckti,composite-clock}smcbsp3_mux_fck@68ti,composite-mux-clock}yhsmcbsp3_fckti,composite-clock}smcbsp4_mux_fck@68ti,composite-mux-clock}yhsmcbsp4_fckti,composite-clock}sclockdomainspinmux@a00 ti,omap3-padconfpinctrl-singley \+ *pinmux_twl4030_vpins _saes@480c5000 ti,omap3-aesaesyH PPABtxrx disabledprm@48306000 ti,omap3-prmyH0`@ clocks+virt_16_8m_ck fixed-clockYs osc_sys_ck@d40 ti,mux-clock} y @s!sys_ck@1270ti,divider-clock}!yp s&sys_clkout1@d70ti,gate-clock}!y pdpll3_x2_ckfixed-factor-clock}"#.dpll3_m2x2_ckfixed-factor-clock}##.s%dpll4_x2_ckfixed-factor-clock}$#.corex2_fckfixed-factor-clock}%#.s'wkup_l4_ickfixed-factor-clock}&#.sVcorex2_d3_fckfixed-factor-clock}'#.scorex2_d5_fckfixed-factor-clock}'#.sclockdomainscm@48004000 ti,omap3-cmyH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clocksHvirt_12m_ck fixed-clocksvirt_13m_ck fixed-clock]@svirt_19200000_ck fixed-clock$svirt_26000000_ck fixed-clocksvirt_38_4m_ck fixed-clockIsdpll4_ck@d00ti,omap3-dpll-per-clock}&&y D 0s$dpll4_m2_ck@d48ti,divider-clock}$?y H s(dpll4_m2x2_mul_ckfixed-factor-clock}(#.s)dpll4_m2x2_ck@d00ti,gate-clock})y 8s*omap_96m_alwon_fckfixed-factor-clock}*#.s1dpll3_ck@d00ti,omap3-dpll-core-clock}&&y @ 0s"dpll3_m3_ck@1140ti,divider-clock}"y@ s+dpll3_m3x2_mul_ckfixed-factor-clock}+#.s,dpll3_m3x2_ck@d00ti,gate-clock}, y 8s-emu_core_alwon_ckfixed-factor-clock}-#.sjsys_altclk fixed-clocks6mcbsp_clks fixed-clocksdpll3_m2_ck@d40ti,divider-clock}"y @ s#core_ckfixed-factor-clock}##.s.dpll1_fck@940ti,divider-clock}.y @ s/dpll1_ck@904ti,omap3-dpll-clock}&/y  $ @ 4sdpll1_x2_ckfixed-factor-clock}#.s0dpll1_x2m2_ck@944ti,divider-clock}0y D sDcm_96m_fckfixed-factor-clock}1#.s2omap_96m_fck@d40 ti,mux-clock}2&y @sMdpll4_m3_ck@e40ti,divider-clock}$ y@ s3dpll4_m3x2_mul_ckfixed-factor-clock}3#.s4dpll4_m3x2_ck@d00ti,gate-clock}4y 8s5omap_54m_fck@d40 ti,mux-clock}56y @s@cm_96m_d2_fckfixed-factor-clock}2#.s7omap_48m_fck@d40 ti,mux-clock}76y @s8omap_12m_fckfixed-factor-clock}8#.sOdpll4_m4_ck@e40ti,divider-clock}$ y@ s9dpll4_m4x2_mul_ckti,fixed-factor-clock}9N\is:dpll4_m4x2_ck@d00ti,gate-clock}:y 8isdpll4_m5_ck@f40ti,divider-clock}$?y@ s;dpll4_m5x2_mul_ckti,fixed-factor-clock};N\is<dpll4_m5x2_ck@d00ti,gate-clock}<y 8isrdpll4_m6_ck@1140ti,divider-clock}$?y@ s=dpll4_m6x2_mul_ckfixed-factor-clock}=#.s>dpll4_m6x2_ck@d00ti,gate-clock}>y 8s?emu_per_alwon_ckfixed-factor-clock}?#.skclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock}.y psAclkout2_src_mux_ck@d70ti,composite-mux-clock}.&2@y psBclkout2_src_ckti,composite-clock}ABsCsys_clkout2@d70ti,divider-clock}C@y p|mpu_ckfixed-factor-clock}D#.sEarm_fck@924ti,divider-clock}Ey $emu_mpu_alwon_ckfixed-factor-clock}E#.sll3_ick@a40ti,divider-clock}.y @ sFl4_ick@a40ti,divider-clock}Fy @ sGrm_ick@c40ti,divider-clock}Gy @ gpt10_gate_fck@a00ti,composite-gate-clock}& y sIgpt10_mux_fck@a40ti,composite-mux-clock}H&y @sJgpt10_fckti,composite-clock}IJgpt11_gate_fck@a00ti,composite-gate-clock}& y sKgpt11_mux_fck@a40ti,composite-mux-clock}H&y @sLgpt11_fckti,composite-clock}KLcore_96m_fckfixed-factor-clock}M#.s mmchs2_fck@a00ti,wait-gate-clock} y smmchs1_fck@a00ti,wait-gate-clock} y si2c3_fck@a00ti,wait-gate-clock} y si2c2_fck@a00ti,wait-gate-clock} y si2c1_fck@a00ti,wait-gate-clock} y smcbsp5_gate_fck@a00ti,composite-gate-clock} y smcbsp1_gate_fck@a00ti,composite-gate-clock} y score_48m_fckfixed-factor-clock}8#.sNmcspi4_fck@a00ti,wait-gate-clock}Ny smcspi3_fck@a00ti,wait-gate-clock}Ny smcspi2_fck@a00ti,wait-gate-clock}Ny smcspi1_fck@a00ti,wait-gate-clock}Ny suart2_fck@a00ti,wait-gate-clock}Ny suart1_fck@a00ti,wait-gate-clock}Ny  score_12m_fckfixed-factor-clock}O#.sPhdq_fck@a00ti,wait-gate-clock}Py score_l3_ickfixed-factor-clock}F#.sQsdrc_ick@a10ti,wait-gate-clock}Qy sgpmc_fckfixed-factor-clock}Q#.core_l4_ickfixed-factor-clock}G#.sRmmchs2_ick@a10ti,omap3-interface-clock}Ry smmchs1_ick@a10ti,omap3-interface-clock}Ry shdq_ick@a10ti,omap3-interface-clock}Ry smcspi4_ick@a10ti,omap3-interface-clock}Ry smcspi3_ick@a10ti,omap3-interface-clock}Ry smcspi2_ick@a10ti,omap3-interface-clock}Ry smcspi1_ick@a10ti,omap3-interface-clock}Ry si2c3_ick@a10ti,omap3-interface-clock}Ry si2c2_ick@a10ti,omap3-interface-clock}Ry si2c1_ick@a10ti,omap3-interface-clock}Ry suart2_ick@a10ti,omap3-interface-clock}Ry suart1_ick@a10ti,omap3-interface-clock}Ry  sgpt11_ick@a10ti,omap3-interface-clock}Ry  sgpt10_ick@a10ti,omap3-interface-clock}Ry  smcbsp5_ick@a10ti,omap3-interface-clock}Ry  smcbsp1_ick@a10ti,omap3-interface-clock}Ry  somapctrl_ick@a10ti,omap3-interface-clock}Ry sdss_tv_fck@e00ti,gate-clock}@ysdss_96m_fck@e00ti,gate-clock}Mysdss2_alwon_fck@e00ti,gate-clock}&ysdummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock}&y sSgpt1_mux_fck@c40ti,composite-mux-clock}H&y @sTgpt1_fckti,composite-clock}STaes2_ick@a10ti,omap3-interface-clock}Ry swkup_32k_fckfixed-factor-clock}H#.sUgpio1_dbck@c00ti,gate-clock}Uy ssha12_ick@a10ti,omap3-interface-clock}Ry swdt2_fck@c00ti,wait-gate-clock}Uy swdt2_ick@c10ti,omap3-interface-clock}Vy swdt1_ick@c10ti,omap3-interface-clock}Vy sgpio1_ick@c10ti,omap3-interface-clock}Vy somap_32ksync_ick@c10ti,omap3-interface-clock}Vy sgpt12_ick@c10ti,omap3-interface-clock}Vy sgpt1_ick@c10ti,omap3-interface-clock}Vy sper_96m_fckfixed-factor-clock}1#.sper_48m_fckfixed-factor-clock}8#.sWuart3_fck@1000ti,wait-gate-clock}Wy sgpt2_gate_fck@1000ti,composite-gate-clock}&ysXgpt2_mux_fck@1040ti,composite-mux-clock}H&y@sYgpt2_fckti,composite-clock}XYgpt3_gate_fck@1000ti,composite-gate-clock}&ysZgpt3_mux_fck@1040ti,composite-mux-clock}H&y@s[gpt3_fckti,composite-clock}Z[gpt4_gate_fck@1000ti,composite-gate-clock}&ys\gpt4_mux_fck@1040ti,composite-mux-clock}H&y@s]gpt4_fckti,composite-clock}\]gpt5_gate_fck@1000ti,composite-gate-clock}&ys^gpt5_mux_fck@1040ti,composite-mux-clock}H&y@s_gpt5_fckti,composite-clock}^_gpt6_gate_fck@1000ti,composite-gate-clock}&ys`gpt6_mux_fck@1040ti,composite-mux-clock}H&y@sagpt6_fckti,composite-clock}`agpt7_gate_fck@1000ti,composite-gate-clock}&ysbgpt7_mux_fck@1040ti,composite-mux-clock}H&y@scgpt7_fckti,composite-clock}bcgpt8_gate_fck@1000ti,composite-gate-clock}& ysdgpt8_mux_fck@1040ti,composite-mux-clock}H&y@segpt8_fckti,composite-clock}degpt9_gate_fck@1000ti,composite-gate-clock}& ysfgpt9_mux_fck@1040ti,composite-mux-clock}H&y@sggpt9_fckti,composite-clock}fgper_32k_alwon_fckfixed-factor-clock}H#.shgpio6_dbck@1000ti,gate-clock}hysgpio5_dbck@1000ti,gate-clock}hysgpio4_dbck@1000ti,gate-clock}hysgpio3_dbck@1000ti,gate-clock}hysgpio2_dbck@1000ti,gate-clock}hy swdt3_fck@1000ti,wait-gate-clock}hy sper_l4_ickfixed-factor-clock}G#.sigpio6_ick@1010ti,omap3-interface-clock}iysgpio5_ick@1010ti,omap3-interface-clock}iysgpio4_ick@1010ti,omap3-interface-clock}iysgpio3_ick@1010ti,omap3-interface-clock}iysgpio2_ick@1010ti,omap3-interface-clock}iy swdt3_ick@1010ti,omap3-interface-clock}iy suart3_ick@1010ti,omap3-interface-clock}iy suart4_ick@1010ti,omap3-interface-clock}iysgpt9_ick@1010ti,omap3-interface-clock}iy sgpt8_ick@1010ti,omap3-interface-clock}iy sgpt7_ick@1010ti,omap3-interface-clock}iysgpt6_ick@1010ti,omap3-interface-clock}iysgpt5_ick@1010ti,omap3-interface-clock}iysgpt4_ick@1010ti,omap3-interface-clock}iysgpt3_ick@1010ti,omap3-interface-clock}iysgpt2_ick@1010ti,omap3-interface-clock}iysmcbsp2_ick@1010ti,omap3-interface-clock}iysmcbsp3_ick@1010ti,omap3-interface-clock}iysmcbsp4_ick@1010ti,omap3-interface-clock}iysmcbsp2_gate_fck@1000ti,composite-gate-clock}ysmcbsp3_gate_fck@1000ti,composite-gate-clock}ysmcbsp4_gate_fck@1000ti,composite-gate-clock}ysemu_src_mux_ck@1140 ti,mux-clock}&jkly@smemu_src_ckti,clkdm-gate-clock}msnpclk_fck@1140ti,divider-clock}ny@ pclkx2_fck@1140ti,divider-clock}ny@ atclk_fck@1140ti,divider-clock}ny@ traceclk_src_fck@1140 ti,mux-clock}&jkly@sotraceclk_fck@1140ti,divider-clock}o y@ secure_32k_fck fixed-clockspgpt12_fckfixed-factor-clock}p#.wdt1_fckfixed-factor-clock}p#.security_l4_ick2fixed-factor-clock}G#.sqaes1_ick@a14ti,omap3-interface-clock}qy rng_ick@a14ti,omap3-interface-clock}qy sha11_ick@a14ti,omap3-interface-clock}qy des1_ick@a14ti,omap3-interface-clock}qy cam_mclk@f00ti,gate-clock}ryicam_ick@f10!ti,omap3-no-wait-interface-clock}Gyscsi2_96m_fck@f00ti,gate-clock} yssecurity_l3_ickfixed-factor-clock}F#.sspka_ick@a14ti,omap3-interface-clock}sy icr_ick@a10ti,omap3-interface-clock}Ry des2_ick@a10ti,omap3-interface-clock}Ry mspro_ick@a10ti,omap3-interface-clock}Ry mailboxes_ick@a10ti,omap3-interface-clock}Ry ssi_l4_ickfixed-factor-clock}G#.szsr1_fck@c00ti,wait-gate-clock}&y s sr2_fck@c00ti,wait-gate-clock}&y s sr_l4_ickfixed-factor-clock}G#.dpll2_fck@40ti,divider-clock}.y@ stdpll2_ck@4ti,omap3-dpll-clock}&ty$@4sudpll2_m2_ck@44ti,divider-clock}uyD sviva2_ck@0ti,wait-gate-clock}vysmodem_fck@a00ti,omap3-interface-clock}&y ssad2d_ick@a10ti,omap3-interface-clock}Fy smad2d_ick@a18ti,omap3-interface-clock}Fy smspro_fck@a00ti,wait-gate-clock} y ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock}'y swssi_ssr_div_fck_3430es2@a40ti,composite-divider-clock}'y @$sxssi_ssr_fck_3430es2ti,composite-clock}wxsyssi_sst_fck_3430es2fixed-factor-clock}y#.shsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clock}Qy sssi_ick_3430es2@a10ti,omap3-ssi-interface-clock}zy susim_gate_fck@c00ti,composite-gate-clock}M y ssys_d2_ckfixed-factor-clock}&#.s|omap_96m_d2_fckfixed-factor-clock}M#.s}omap_96m_d4_fckfixed-factor-clock}M#.s~omap_96m_d8_fckfixed-factor-clock}M#.somap_96m_d10_fckfixed-factor-clock}M#. sdpll5_m2_d4_ckfixed-factor-clock}{#.sdpll5_m2_d8_ckfixed-factor-clock}{#.sdpll5_m2_d16_ckfixed-factor-clock}{#.sdpll5_m2_d20_ckfixed-factor-clock}{#.susim_mux_fck@c40ti,composite-mux-clock(}&|}~y @ susim_fckti,composite-clock}usim_ick@c10ti,omap3-interface-clock}Vy  sdpll5_ck@d04ti,omap3-dpll-clock}&&y  $ L 4sdpll5_m2_ck@d50ti,divider-clock}y P s{sgx_gate_fck@b00ti,composite-gate-clock}.y score_d3_ckfixed-factor-clock}.#.score_d4_ckfixed-factor-clock}.#.score_d6_ckfixed-factor-clock}.#.somap_192m_alwon_fckfixed-factor-clock}*#.score_d2_ckfixed-factor-clock}.#.ssgx_mux_fck@b40ti,composite-mux-clock }2y @ssgx_fckti,composite-clock}s sgx_ick@b10ti,wait-gate-clock}Fy scpefuse_fck@a08ti,gate-clock}&y sts_fck@a08ti,gate-clock}Hy susbtll_fck@a08ti,wait-gate-clock}{y susbtll_ick@a18ti,omap3-interface-clock}Ry smmchs3_ick@a10ti,omap3-interface-clock}Ry smmchs3_fck@a00ti,wait-gate-clock} y sdss1_alwon_fck_3430es2@e00ti,dss-gate-clock}yisdss_ick_3430es2@e10ti,omap3-dss-interface-clock}Gysusbhost_120m_fck@1400ti,gate-clock}{ysusbhost_48m_fck@1400ti,dss-gate-clock}8ysusbhost_ick@1410ti,omap3-dss-interface-clock}Gysclockdomainscore_l3_clkdmti,clockdomain}dpll3_clkdmti,clockdomain}"dpll1_clkdmti,clockdomain}per_clkdmti,clockdomainh}emu_clkdmti,clockdomain}ndpll4_clkdmti,clockdomain}$wkup_clkdmti,clockdomain$}dss_clkdmti,clockdomain}core_l4_clkdmti,clockdomain}cam_clkdmti,clockdomain}iva2_clkdmti,clockdomain}dpll2_clkdmti,clockdomain}ud2d_clkdmti,clockdomain }dpll5_clkdmti,clockdomain}sgx_clkdmti,clockdomain}usbhost_clkdmti,clockdomain }counter@48320000ti,omap-counter32kyH2  counter_32kinterrupt-controller@48200000ti,omap3-intcyH sdma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmayH`  `dmasgpio@48310000ti,omap3-gpioyH1gpio1gpio@49050000ti,omap3-gpioyIgpio2gpio@49052000ti,omap3-gpioyI gpio3gpio@49054000ti,omap3-gpioyI@ gpio4gpio@49056000ti,omap3-gpioyI`!gpio5sgpio@49058000ti,omap3-gpioyI"gpio6sserial@4806a000ti,omap3-uartyH H12txrxuart1lserial@4806c000ti,omap3-uartyHI34txrxuart2lserial@49020000ti,omap3-uartyIJ56txrxuart3lGdefaultUi2c@48070000 ti,omap3-i2cyH8txrx+i2c1'@twl@48yH  ti,twl4030GdefaultUaudioti,twl4030-audiocodecrtcti,twl4030-rtc bciti,twl4030-bci 3A Mvacwatchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2 vdd_ehciw@w@^regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1 ' sregulator-vdacti,twl4030-vdacw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1:0sregulator-vmmc2ti,twl4030-vmmc2:0regulator-vusb1v5ti,twl4030-vusb1v5sregulator-vusb1v8ti,twl4030-vusb1v8sregulator-vusb3v1ti,twl4030-vusb3v1sregulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2w@w@^regulator-vsimti,twl4030-vsimw@-sgpioti,twl4030-gpior~stwl4030-usbti,twl4030-usb spwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypadmadcti,twl4030-madcsi2c@48072000 ti,omap3-i2cyH 9txrx+i2c2 disabledi2c@48060000 ti,omap3-i2cyH=txrx+i2c3GdefaultUmailbox@48094000ti,omap3-mailboxmailboxyH @ 2dsp D Ospi@48098000ti,omap2-mcspiyH A+mcspi1Z@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3GdefaultUspidev@0spidevhlyzspi@4809a000ti,omap2-mcspiyH B+mcspi2Z +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiyH [+mcspi3Z tx0rx0tx1rx1GdefaultUspidev@0spidevhlyzspi@480ba000ti,omap2-mcspiyH 0+mcspi4ZFGtx0rx01w@480b2000 ti,omap3-1wyH :hdq1wmmc@4809c000ti,omap3-hsmmcyH Smmc1=>txrxGdefaultU mmc@480b4000ti,omap3-hsmmcyH @Vmmc2/0txrxGdefaultUmmc@480ad000ti,omap3-hsmmcyH ^mmc3MNtxrx disabledmmu@480bd400ti,omap2-iommuyH mmu_isps mmu@5d000000ti,omap2-iommuy]mmu_iva disabledwdt@48314000 ti,omap3-wdtyH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspyH@mpu ;< commontxrx!mcbsp1 txrx}fck disabledmcbsp@49022000ti,omap3-mcbspyI I mpusidetone>?commontxrxsidetone!mcbsp2mcbsp2_sidetone!"txrx}fckickokaysmcbsp@49024000ti,omap3-mcbspyI@I mpusidetoneYZcommontxrxsidetone!mcbsp3mcbsp3_sidetonetxrx}fckickokayGdefaultUmcbsp@49026000ti,omap3-mcbspyI`mpu 67 commontxrx!mcbsp4txrx}fck0 disabledmcbsp@48096000ti,omap3-mcbspyH `mpu QR commontxrx!mcbsp5txrx}fck disabledsham@480c3000ti,omap3-shamshamyH 0d1Erx disabledtimer@48318000ti,omap3430-timeryH1%timer1Atimer@49032000ti,omap3430-timeryI &timer2timer@49034000ti,omap3430-timeryI@'timer3timer@49036000ti,omap3430-timeryI`(timer4timer@49038000ti,omap3430-timeryI)timer5Ptimer@4903a000ti,omap3430-timeryI*timer6Ptimer@4903c000ti,omap3430-timeryI+timer7Ptimer@4903e000ti,omap3430-timeryI,timer8]Ptimer@49040000ti,omap3430-timeryI-timer9]timer@48086000ti,omap3430-timeryH`.timer10]timer@48088000ti,omap3430-timeryH/timer11]timer@48304000ti,omap3430-timeryH0@_timer12Ajusbhstll@48062000 ti,usbhs-tllyH N usb_tll_hsusbhshost@48064000ti,usbhs-hostyH@ usb_host_hs+ zehci-phyohci@48064400ti,ohci-omap3yHDLehci@48064800 ti,ehci-omapyHHMgpmc@6e000000ti,omap3430-gpmcgpmcynrxtx+0snand@0,0ti,omap2-nand y sw$$#2E$Xf0uHH6+x-loader@0 X-Loaderybootloaders@80000U-Bootybootloaders_env@260000 U-Boot Envy&kernel@280000Kernely(@filesystem@680000 File Systemyhusb_otg_hs@480ab000ti,omap3-musbyH \]mcdma usb_otg_hs  usb2-phy2dss@48050000 ti,omap3-dssyHok dss_core}fck+GdefaultUdispc@48050400ti,omap3-dispcyH dss_dispc}fckencoder@4804fc00 ti,omap3-dsiyHH@H protophypll disabled dss_dsi1} fcksys_clkencoder@48050800ti,omap3-rfbiyH disabled dss_rfbi}fckickencoder@48050c00ti,omap3-vencyH  disabled dss_venc}fckportendpoint.sssi-controller@48058000 ti,omap3-ssissiokyHHsysgddGgdd_mpu+ }y ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portyHHtxrxCDssi-port@4805b000ti,omap3-ssi-portyHHtxrxEFpinmux@480025d8 ti,omap3-padconfpinctrl-singleyH%$+ *isp@480bc000 ti,omap3-ispyH H |9 { l@ports+bandgap@48002524yH%$ti,omap34xx-bandgapLs target-module@480cb000ti,sysc-omap3430-srti,syscsmartreflex_coreyH $syscb} fck+ H smartreflex@0ti,omap3-smartreflex-coreytarget-module@480c9000ti,sysc-omap3430-srti,syscsmartreflex_mpu_ivayH $syscb} fck+ H smartreflex@480c9000ti,omap3-smartreflex-mpu-ivaytarget-module@50000000ti,sysc-omap2ti,syscyPrev} fckick+ P@thermal-zonescpu_thermaloN  memory@80000000mmemoryyhsusb2_power_regregulator-fixed hsusb2_vbus2Z2Z pshsusb2_phyusb-nop-xceiv ssoundti,omap-twl4030 omap3beagleregulator-mmc2-sdio-poweronregulator-fixedregulator-mmc2-sdio-poweron00 'sgpio_poweroffGdefaultUgpio-poweroff display panel-dpilcdGdefaultU  portendpointspanel-timingP  (V%/; HR_lvbacklightgpio-backlightGdefaultU   compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-pointscpu0-supplyinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinsphandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesstatusclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyio-channelsio-channel-namesregulator-always-onti,use-ledsti,pullupsti,pulldownsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencyspi-cphati,dual-voltpbias-supplyvmmc-supplyvqmmc-supplycd-gpiosbus-widthnon-removablecap-power-off-card#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-size#sound-dai-cellsti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,wr-access-nslabelmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerremote-endpointdata-linesiommusti,phy-type#thermal-sensor-cellsti,sysc-maskpolling-delay-passivepolling-delaycoefficientsthermal-sensorsgpiostartup-delay-usreset-gpiosvcc-supplyti,modelti,mcbspenable-gpioshactivevactivehfront-porchhback-porchhsync-lenvback-porchvfront-porchvsync-lenhsync-activevsync-activede-activepixelclk-activedefault-on