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@r1dpll4_m4x2_mul_ckti,fixed-factor-clock1FTar2dpll4_m4x2_ck@d00ti,gate-clock2 0ardpll4_m5_ck@f40ti,divider-clock?@r3dpll4_m5x2_mul_ckti,fixed-factor-clock3FTar4dpll4_m5x2_ck@d00ti,hsdiv-gate-clock4 0arjdpll4_m6_ck@1140ti,divider-clock?@r5dpll4_m6x2_mul_ckfixed-factor-clock5&r6dpll4_m6x2_ck@d00ti,hsdiv-gate-clock6 0r7emu_per_alwon_ckfixed-factor-clock7&rcclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock& pr9clkout2_src_mux_ck@d70ti,composite-mux-clock&*8 pr:clkout2_src_ckti,composite-clock9:r;sys_clkout2@d70ti,divider-clock;@ ptmpu_ckfixed-factor-clock<&r=arm_fck@924ti,divider-clock= $emu_mpu_alwon_ckfixed-factor-clock=&rdl3_ick@a40ti,divider-clock& @r>l4_ick@a40ti,divider-clock> @r?rm_ick@c40ti,divider-clock? @gpt10_gate_fck@a00ti,composite-gate-clock  rAgpt10_mux_fck@a40ti,composite-mux-clock@ @rBgpt10_fckti,composite-clockABgpt11_gate_fck@a00ti,composite-gate-clock  rCgpt11_mux_fck@a40ti,composite-mux-clock@ @rDgpt11_fckti,composite-clockCDcore_96m_fckfixed-factor-clockE&rmmchs2_fck@a00ti,wait-gate-clock rmmchs1_fck@a00ti,wait-gate-clock ri2c3_fck@a00ti,wait-gate-clock ri2c2_fck@a00ti,wait-gate-clock ri2c1_fck@a00ti,wait-gate-clock rmcbsp5_gate_fck@a00ti,composite-gate-clock  rmcbsp1_gate_fck@a00ti,composite-gate-clock  r core_48m_fckfixed-factor-clock0&rFmcspi4_fck@a00ti,wait-gate-clockF rmcspi3_fck@a00ti,wait-gate-clockF rmcspi2_fck@a00ti,wait-gate-clockF rmcspi1_fck@a00ti,wait-gate-clockF ruart2_fck@a00ti,wait-gate-clockF ruart1_fck@a00ti,wait-gate-clockF  rcore_12m_fckfixed-factor-clockG&rHhdq_fck@a00ti,wait-gate-clockH rcore_l3_ickfixed-factor-clock>&rIsdrc_ick@a10ti,wait-gate-clockI rgpmc_fckfixed-factor-clockI&core_l4_ickfixed-factor-clock?&rJmmchs2_ick@a10ti,omap3-interface-clockJ rmmchs1_ick@a10ti,omap3-interface-clockJ rhdq_ick@a10ti,omap3-interface-clockJ rmcspi4_ick@a10ti,omap3-interface-clockJ rmcspi3_ick@a10ti,omap3-interface-clockJ rmcspi2_ick@a10ti,omap3-interface-clockJ rmcspi1_ick@a10ti,omap3-interface-clockJ ri2c3_ick@a10ti,omap3-interface-clockJ ri2c2_ick@a10ti,omap3-interface-clockJ ri2c1_ick@a10ti,omap3-interface-clockJ ruart2_ick@a10ti,omap3-interface-clockJ ruart1_ick@a10ti,omap3-interface-clockJ  rgpt11_ick@a10ti,omap3-interface-clockJ  rgpt10_ick@a10ti,omap3-interface-clockJ  rmcbsp5_ick@a10ti,omap3-interface-clockJ  rmcbsp1_ick@a10ti,omap3-interface-clockJ  romapctrl_ick@a10ti,omap3-interface-clockJ rdss_tv_fck@e00ti,gate-clock8rdss_96m_fck@e00ti,gate-clockErdss2_alwon_fck@e00ti,gate-clockrdummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock rKgpt1_mux_fck@c40ti,composite-mux-clock@ @rLgpt1_fckti,composite-clockKLaes2_ick@a10ti,omap3-interface-clockJ rwkup_32k_fckfixed-factor-clock@&rMgpio1_dbck@c00ti,gate-clockM rsha12_ick@a10ti,omap3-interface-clockJ rwdt2_fck@c00ti,wait-gate-clockM rwdt2_ick@c10ti,omap3-interface-clockN rwdt1_ick@c10ti,omap3-interface-clockN rgpio1_ick@c10ti,omap3-interface-clockN romap_32ksync_ick@c10ti,omap3-interface-clockN rgpt12_ick@c10ti,omap3-interface-clockN rgpt1_ick@c10ti,omap3-interface-clockN rper_96m_fckfixed-factor-clock)&r per_48m_fckfixed-factor-clock0&rOuart3_fck@1000ti,wait-gate-clockO rgpt2_gate_fck@1000ti,composite-gate-clockrPgpt2_mux_fck@1040ti,composite-mux-clock@@rQgpt2_fckti,composite-clockPQgpt3_gate_fck@1000ti,composite-gate-clockrRgpt3_mux_fck@1040ti,composite-mux-clock@@rSgpt3_fckti,composite-clockRSgpt4_gate_fck@1000ti,composite-gate-clockrTgpt4_mux_fck@1040ti,composite-mux-clock@@rUgpt4_fckti,composite-clockTUgpt5_gate_fck@1000ti,composite-gate-clockrVgpt5_mux_fck@1040ti,composite-mux-clock@@rWgpt5_fckti,composite-clockVWgpt6_gate_fck@1000ti,composite-gate-clockrXgpt6_mux_fck@1040ti,composite-mux-clock@@rYgpt6_fckti,composite-clockXYgpt7_gate_fck@1000ti,composite-gate-clockrZgpt7_mux_fck@1040ti,composite-mux-clock@@r[gpt7_fckti,composite-clockZ[gpt8_gate_fck@1000ti,composite-gate-clock r\gpt8_mux_fck@1040ti,composite-mux-clock@@r]gpt8_fckti,composite-clock\]gpt9_gate_fck@1000ti,composite-gate-clock r^gpt9_mux_fck@1040ti,composite-mux-clock@@r_gpt9_fckti,composite-clock^_per_32k_alwon_fckfixed-factor-clock@&r`gpio6_dbck@1000ti,gate-clock`rgpio5_dbck@1000ti,gate-clock`rgpio4_dbck@1000ti,gate-clock`rgpio3_dbck@1000ti,gate-clock`rgpio2_dbck@1000ti,gate-clock` rwdt3_fck@1000ti,wait-gate-clock` rper_l4_ickfixed-factor-clock?&ragpio6_ick@1010ti,omap3-interface-clockargpio5_ick@1010ti,omap3-interface-clockargpio4_ick@1010ti,omap3-interface-clockargpio3_ick@1010ti,omap3-interface-clockargpio2_ick@1010ti,omap3-interface-clocka rwdt3_ick@1010ti,omap3-interface-clocka ruart3_ick@1010ti,omap3-interface-clocka ruart4_ick@1010ti,omap3-interface-clockargpt9_ick@1010ti,omap3-interface-clocka rgpt8_ick@1010ti,omap3-interface-clocka rgpt7_ick@1010ti,omap3-interface-clockargpt6_ick@1010ti,omap3-interface-clockargpt5_ick@1010ti,omap3-interface-clockargpt4_ick@1010ti,omap3-interface-clockargpt3_ick@1010ti,omap3-interface-clockargpt2_ick@1010ti,omap3-interface-clockarmcbsp2_ick@1010ti,omap3-interface-clockarmcbsp3_ick@1010ti,omap3-interface-clockarmcbsp4_ick@1010ti,omap3-interface-clockarmcbsp2_gate_fck@1000ti,composite-gate-clockr mcbsp3_gate_fck@1000ti,composite-gate-clockrmcbsp4_gate_fck@1000ti,composite-gate-clockremu_src_mux_ck@1140 ti,mux-clockbcd@reemu_src_ckti,clkdm-gate-clockerfpclk_fck@1140ti,divider-clockf@pclkx2_fck@1140ti,divider-clockf@atclk_fck@1140ti,divider-clockf@traceclk_src_fck@1140 ti,mux-clockbcd@rgtraceclk_fck@1140ti,divider-clockg @secure_32k_fck fixed-clockrhgpt12_fckfixed-factor-clockh&wdt1_fckfixed-factor-clockh&security_l4_ick2fixed-factor-clock?&riaes1_ick@a14ti,omap3-interface-clocki rng_ick@a14ti,omap3-interface-clocki sha11_ick@a14ti,omap3-interface-clocki des1_ick@a14ti,omap3-interface-clocki cam_mclk@f00ti,gate-clockjacam_ick@f10!ti,omap3-no-wait-interface-clock?rcsi2_96m_fck@f00ti,gate-clockrsecurity_l3_ickfixed-factor-clock>&rkpka_ick@a14ti,omap3-interface-clockk icr_ick@a10ti,omap3-interface-clockJ des2_ick@a10ti,omap3-interface-clockJ mspro_ick@a10ti,omap3-interface-clockJ mailboxes_ick@a10ti,omap3-interface-clockJ ssi_l4_ickfixed-factor-clock?&rrsr1_fck@c00ti,wait-gate-clock rsr2_fck@c00ti,wait-gate-clock rsr_l4_ickfixed-factor-clock?&dpll2_fck@40ti,divider-clock&@rldpll2_ck@4ti,omap3-dpll-clockl$@4rmdpll2_m2_ck@44ti,divider-clockmDrniva2_ck@0ti,wait-gate-clocknrmodem_fck@a00ti,omap3-interface-clock rsad2d_ick@a10ti,omap3-interface-clock> rmad2d_ick@a18ti,omap3-interface-clock> rmspro_fck@a00ti,wait-gate-clock ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock rossi_ssr_div_fck_3430es2@a40ti,composite-divider-clock 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Vrtwl4030-usbti,twl4030-usb bp~rpwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypadmadcti,twl4030-madcri2c@48072000 ti,omap3-i2cH 9txrx+i2c2i2c@48060000 ti,omap3-i2cH=txrx+i2c3FdefaultTmailbox@48094000ti,omap3-mailboxmailboxH @dsp  spi@48098000ti,omap2-mcspiH A+mcspi1&@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap2-mcspiH B+mcspi2& +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiH [+mcspi3& tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiH 0+mcspi4&FGtx0rx01w@480b2000 ti,omap3-1wH :hdq1wmmc@4809c000ti,omap3-hsmmcH Smmc14=>txrxAFdefaultTNZj tmmc@480b4000ti,omap3-hsmmcH @Vmmc2/0txrxFdefaultTN}jmmc@480ad000ti,omap3-hsmmcH ^mmc3MNtxrx disabledmmu@480bd400ti,omap2-iommuH mmu_isprmmu@5d000000ti,omap2-iommu]mmu_iva disabledwdt@48314000 ti,omap3-wdtH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspH@mpu ;< commontxrxmcbsp1 txrxfck disabledmcbsp@49022000ti,omap3-mcbspI I mpusidetone>?commontxrxsidetonemcbsp2mcbsp2_sidetone!"txrxfckickokayFdefaultTr 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compatibleinterrupt-parent#address-cells#size-cellsmodelstdout-pathi2c0i2c1i2c2serial0serial1serial2serial3device_typeregclocksclock-namesclock-latencyoperating-pointsinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinsphandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyio-channelsio-channel-namesti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplyvmmc_aux-supplybus-widthcd-gpiosmmc-pwrseqnon-removablestatus#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-size#sound-dai-cellsti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinslinux,mtd-namenand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nsgpmc,sync-readgpmc,sync-writegpmc,burst-lengthgpmc,burst-wrapgpmc,burst-readgpmc,burst-writegpmc,mux-add-datagpmc,oe-on-nsgpmc,we-on-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-type#thermal-sensor-cellsti,sysc-maskti,sysc-sidleti,sysc-midlepolling-delay-passivepolling-delaycoefficientsthermal-sensorsti,modelti,mcbspregulator-always-onlabeldefault-statereset-gpios