8( ati,omap3-ldpti,omap3 +!7TI OMAP3430 LDP (Zoom1 Labrador)chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000 d/displaycpus+cpu@0arm,cortex-a8mcpuy}cpu(HАg8 Odp` 'ppmu@54000000arm,cortex-a8-pmuyTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busyh +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-busy + pinmux@30 ti,omap3-padconfpinctrl-singley08+ *Gpinmux_twl4030_pinsOAGpinmux_gpio_key_pinsHOGpinmux_musb_pins`Orz|~vxtGpinmux_mmc1_pins0OGscm_conf@270sysconsimple-busyp0+ p0Gpbias_regulator@2b0ti,pbias-omap3ti,pbias-omapycpbias_mmc_omap2430jpbias_mmc_omap2430yw@-Gclocks+mcbsp5_mux_fck@68ti,composite-mux-clock}yhGmcbsp5_fckti,composite-clock}Gmcbsp1_mux_fck@4ti,composite-mux-clock}yG mcbsp1_fckti,composite-clock} Gmcbsp2_mux_fck@4ti,composite-mux-clock} yG mcbsp2_fckti,composite-clock} Gmcbsp3_mux_fck@68ti,composite-mux-clock} yhGmcbsp3_fckti,composite-clock}Gmcbsp4_mux_fck@68ti,composite-mux-clock} yhGmcbsp4_fckti,composite-clock}Gclockdomainspinmux@a00 ti,omap3-padconfpinctrl-singley \+ *pinmux_twl4030_vpins OGaes@480c5000 ti,omap3-aesaesyH PPABtxrxprm@48306000 ti,omap3-prmyH0`@ clocks+virt_16_8m_ck fixed-clockYGosc_sys_ck@d40 ti,mux-clock}y @Gsys_ck@1270ti,divider-clock}ypGsys_clkout1@d70ti,gate-clock}y pdpll3_x2_ckfixed-factor-clock}dpll3_m2x2_ckfixed-factor-clock}Gdpll4_x2_ckfixed-factor-clock}corex2_fckfixed-factor-clock}Gwkup_l4_ickfixed-factor-clock}GNcorex2_d3_fckfixed-factor-clock}Gcorex2_d5_fckfixed-factor-clock}Gclockdomainscm@48004000 ti,omap3-cmyH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clockG@virt_12m_ck fixed-clockGvirt_13m_ck fixed-clock]@Gvirt_19200000_ck fixed-clock$Gvirt_26000000_ck fixed-clockGvirt_38_4m_ck fixed-clockIGdpll4_ck@d00ti,omap3-dpll-per-clock}y D 0Gdpll4_m2_ck@d48ti,divider-clock}?y HG dpll4_m2x2_mul_ckfixed-factor-clock} G!dpll4_m2x2_ck@d00ti,gate-clock}!y G"omap_96m_alwon_fckfixed-factor-clock}"G)dpll3_ck@d00ti,omap3-dpll-core-clock}y @ 0Gdpll3_m3_ck@1140ti,divider-clock}y@G#dpll3_m3x2_mul_ckfixed-factor-clock}#G$dpll3_m3x2_ck@d00ti,gate-clock}$ y G%emu_core_alwon_ckfixed-factor-clock}%Gbsys_altclk fixed-clockG.mcbsp_clks fixed-clockGdpll3_m2_ck@d40ti,divider-clock}y @Gcore_ckfixed-factor-clock}G&dpll1_fck@940ti,divider-clock}&y @G'dpll1_ck@904ti,omap3-dpll-clock}'y  $ @ 4Gdpll1_x2_ckfixed-factor-clock}G(dpll1_x2m2_ck@944ti,divider-clock}(y DG<cm_96m_fckfixed-factor-clock})G*omap_96m_fck@d40 ti,mux-clock}*y @GEdpll4_m3_ck@e40ti,divider-clock} y@G+dpll4_m3x2_mul_ckfixed-factor-clock}+G,dpll4_m3x2_ck@d00ti,gate-clock},y G-omap_54m_fck@d40 ti,mux-clock}-.y @G8cm_96m_d2_fckfixed-factor-clock}*G/omap_48m_fck@d40 ti,mux-clock}/.y @G0omap_12m_fckfixed-factor-clock}0GGdpll4_m4_ck@e40ti,divider-clock} y@G1dpll4_m4x2_mul_ckti,fixed-factor-clock}1/=JG2dpll4_m4x2_ck@d00ti,gate-clock}2y JGdpll4_m5_ck@f40ti,divider-clock}?y@G3dpll4_m5x2_mul_ckti,fixed-factor-clock}3/=JG4dpll4_m5x2_ck@d00ti,gate-clock}4y JGjdpll4_m6_ck@1140ti,divider-clock}?y@G5dpll4_m6x2_mul_ckfixed-factor-clock}5G6dpll4_m6x2_ck@d00ti,gate-clock}6y G7emu_per_alwon_ckfixed-factor-clock}7Gcclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock}&y pG9clkout2_src_mux_ck@d70ti,composite-mux-clock}&*8y pG:clkout2_src_ckti,composite-clock}9:G;sys_clkout2@d70ti,divider-clock};@y p]mpu_ckfixed-factor-clock}<G=arm_fck@924ti,divider-clock}=y $emu_mpu_alwon_ckfixed-factor-clock}=Gdl3_ick@a40ti,divider-clock}&y @G>l4_ick@a40ti,divider-clock}>y @G?rm_ick@c40ti,divider-clock}?y @gpt10_gate_fck@a00ti,composite-gate-clock} y GAgpt10_mux_fck@a40ti,composite-mux-clock}@y @GBgpt10_fckti,composite-clock}ABgpt11_gate_fck@a00ti,composite-gate-clock} y GCgpt11_mux_fck@a40ti,composite-mux-clock}@y @GDgpt11_fckti,composite-clock}CDcore_96m_fckfixed-factor-clock}EGmmchs2_fck@a00ti,wait-gate-clock}y Gmmchs1_fck@a00ti,wait-gate-clock}y Gi2c3_fck@a00ti,wait-gate-clock}y Gi2c2_fck@a00ti,wait-gate-clock}y Gi2c1_fck@a00ti,wait-gate-clock}y Gmcbsp5_gate_fck@a00ti,composite-gate-clock} y Gmcbsp1_gate_fck@a00ti,composite-gate-clock} y G core_48m_fckfixed-factor-clock}0GFmcspi4_fck@a00ti,wait-gate-clock}Fy Gmcspi3_fck@a00ti,wait-gate-clock}Fy Gmcspi2_fck@a00ti,wait-gate-clock}Fy Gmcspi1_fck@a00ti,wait-gate-clock}Fy Guart2_fck@a00ti,wait-gate-clock}Fy Guart1_fck@a00ti,wait-gate-clock}Fy  Gcore_12m_fckfixed-factor-clock}GGHhdq_fck@a00ti,wait-gate-clock}Hy Gcore_l3_ickfixed-factor-clock}>GIsdrc_ick@a10ti,wait-gate-clock}Iy Ggpmc_fckfixed-factor-clock}Icore_l4_ickfixed-factor-clock}?GJmmchs2_ick@a10ti,omap3-interface-clock}Jy Gmmchs1_ick@a10ti,omap3-interface-clock}Jy Ghdq_ick@a10ti,omap3-interface-clock}Jy Gmcspi4_ick@a10ti,omap3-interface-clock}Jy Gmcspi3_ick@a10ti,omap3-interface-clock}Jy Gmcspi2_ick@a10ti,omap3-interface-clock}Jy Gmcspi1_ick@a10ti,omap3-interface-clock}Jy Gi2c3_ick@a10ti,omap3-interface-clock}Jy Gi2c2_ick@a10ti,omap3-interface-clock}Jy Gi2c1_ick@a10ti,omap3-interface-clock}Jy Guart2_ick@a10ti,omap3-interface-clock}Jy Guart1_ick@a10ti,omap3-interface-clock}Jy  Ggpt11_ick@a10ti,omap3-interface-clock}Jy  Ggpt10_ick@a10ti,omap3-interface-clock}Jy  Gmcbsp5_ick@a10ti,omap3-interface-clock}Jy  Gmcbsp1_ick@a10ti,omap3-interface-clock}Jy  Gomapctrl_ick@a10ti,omap3-interface-clock}Jy Gdss_tv_fck@e00ti,gate-clock}8yGdss_96m_fck@e00ti,gate-clock}EyGdss2_alwon_fck@e00ti,gate-clock}yGdummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock}y GKgpt1_mux_fck@c40ti,composite-mux-clock}@y @GLgpt1_fckti,composite-clock}KLaes2_ick@a10ti,omap3-interface-clock}Jy Gwkup_32k_fckfixed-factor-clock}@GMgpio1_dbck@c00ti,gate-clock}My Gsha12_ick@a10ti,omap3-interface-clock}Jy Gwdt2_fck@c00ti,wait-gate-clock}My Gwdt2_ick@c10ti,omap3-interface-clock}Ny Gwdt1_ick@c10ti,omap3-interface-clock}Ny Ggpio1_ick@c10ti,omap3-interface-clock}Ny Gomap_32ksync_ick@c10ti,omap3-interface-clock}Ny Ggpt12_ick@c10ti,omap3-interface-clock}Ny Ggpt1_ick@c10ti,omap3-interface-clock}Ny Gper_96m_fckfixed-factor-clock})G per_48m_fckfixed-factor-clock}0GOuart3_fck@1000ti,wait-gate-clock}Oy Ggpt2_gate_fck@1000ti,composite-gate-clock}yGPgpt2_mux_fck@1040ti,composite-mux-clock}@y@GQgpt2_fckti,composite-clock}PQgpt3_gate_fck@1000ti,composite-gate-clock}yGRgpt3_mux_fck@1040ti,composite-mux-clock}@y@GSgpt3_fckti,composite-clock}RSgpt4_gate_fck@1000ti,composite-gate-clock}yGTgpt4_mux_fck@1040ti,composite-mux-clock}@y@GUgpt4_fckti,composite-clock}TUgpt5_gate_fck@1000ti,composite-gate-clock}yGVgpt5_mux_fck@1040ti,composite-mux-clock}@y@GWgpt5_fckti,composite-clock}VWgpt6_gate_fck@1000ti,composite-gate-clock}yGXgpt6_mux_fck@1040ti,composite-mux-clock}@y@GYgpt6_fckti,composite-clock}XYgpt7_gate_fck@1000ti,composite-gate-clock}yGZgpt7_mux_fck@1040ti,composite-mux-clock}@y@G[gpt7_fckti,composite-clock}Z[gpt8_gate_fck@1000ti,composite-gate-clock} yG\gpt8_mux_fck@1040ti,composite-mux-clock}@y@G]gpt8_fckti,composite-clock}\]gpt9_gate_fck@1000ti,composite-gate-clock} yG^gpt9_mux_fck@1040ti,composite-mux-clock}@y@G_gpt9_fckti,composite-clock}^_per_32k_alwon_fckfixed-factor-clock}@G`gpio6_dbck@1000ti,gate-clock}`yGgpio5_dbck@1000ti,gate-clock}`yGgpio4_dbck@1000ti,gate-clock}`yGgpio3_dbck@1000ti,gate-clock}`yGgpio2_dbck@1000ti,gate-clock}`y Gwdt3_fck@1000ti,wait-gate-clock}`y Gper_l4_ickfixed-factor-clock}?Gagpio6_ick@1010ti,omap3-interface-clock}ayGgpio5_ick@1010ti,omap3-interface-clock}ayGgpio4_ick@1010ti,omap3-interface-clock}ayGgpio3_ick@1010ti,omap3-interface-clock}ayGgpio2_ick@1010ti,omap3-interface-clock}ay Gwdt3_ick@1010ti,omap3-interface-clock}ay Guart3_ick@1010ti,omap3-interface-clock}ay Guart4_ick@1010ti,omap3-interface-clock}ayGgpt9_ick@1010ti,omap3-interface-clock}ay Ggpt8_ick@1010ti,omap3-interface-clock}ay Ggpt7_ick@1010ti,omap3-interface-clock}ayGgpt6_ick@1010ti,omap3-interface-clock}ayGgpt5_ick@1010ti,omap3-interface-clock}ayGgpt4_ick@1010ti,omap3-interface-clock}ayGgpt3_ick@1010ti,omap3-interface-clock}ayGgpt2_ick@1010ti,omap3-interface-clock}ayGmcbsp2_ick@1010ti,omap3-interface-clock}ayGmcbsp3_ick@1010ti,omap3-interface-clock}ayGmcbsp4_ick@1010ti,omap3-interface-clock}ayGmcbsp2_gate_fck@1000ti,composite-gate-clock}yG mcbsp3_gate_fck@1000ti,composite-gate-clock}yGmcbsp4_gate_fck@1000ti,composite-gate-clock}yGemu_src_mux_ck@1140 ti,mux-clock}bcdy@Geemu_src_ckti,clkdm-gate-clock}eGfpclk_fck@1140ti,divider-clock}fy@pclkx2_fck@1140ti,divider-clock}fy@atclk_fck@1140ti,divider-clock}fy@traceclk_src_fck@1140 ti,mux-clock}bcdy@Ggtraceclk_fck@1140ti,divider-clock}g y@secure_32k_fck fixed-clockGhgpt12_fckfixed-factor-clock}hwdt1_fckfixed-factor-clock}hsecurity_l4_ick2fixed-factor-clock}?Giaes1_ick@a14ti,omap3-interface-clock}iy rng_ick@a14ti,omap3-interface-clock}iy sha11_ick@a14ti,omap3-interface-clock}iy des1_ick@a14ti,omap3-interface-clock}iy cam_mclk@f00ti,gate-clock}jyJcam_ick@f10!ti,omap3-no-wait-interface-clock}?yGcsi2_96m_fck@f00ti,gate-clock}yGsecurity_l3_ickfixed-factor-clock}>Gkpka_ick@a14ti,omap3-interface-clock}ky icr_ick@a10ti,omap3-interface-clock}Jy des2_ick@a10ti,omap3-interface-clock}Jy mspro_ick@a10ti,omap3-interface-clock}Jy mailboxes_ick@a10ti,omap3-interface-clock}Jy ssi_l4_ickfixed-factor-clock}?Grsr1_fck@c00ti,wait-gate-clock}y Gsr2_fck@c00ti,wait-gate-clock}y Gsr_l4_ickfixed-factor-clock}?dpll2_fck@40ti,divider-clock}&y@Gldpll2_ck@4ti,omap3-dpll-clock}ly$@4sGmdpll2_m2_ck@44ti,divider-clock}myDGniva2_ck@0ti,wait-gate-clock}nyGmodem_fck@a00ti,omap3-interface-clock}y Gsad2d_ick@a10ti,omap3-interface-clock}>y Gmad2d_ick@a18ti,omap3-interface-clock}>y Gmspro_fck@a00ti,wait-gate-clock}y ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock}y Gossi_ssr_div_fck_3430es2@a40ti,composite-divider-clock}y @$Gpssi_ssr_fck_3430es2ti,composite-clock}opGqssi_sst_fck_3430es2fixed-factor-clock}qGhsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clock}Iy Gssi_ick_3430es2@a10ti,omap3-ssi-interface-clock}ry Gusim_gate_fck@c00ti,composite-gate-clock}E y G}sys_d2_ckfixed-factor-clock}Gtomap_96m_d2_fckfixed-factor-clock}EGuomap_96m_d4_fckfixed-factor-clock}EGvomap_96m_d8_fckfixed-factor-clock}EGwomap_96m_d10_fckfixed-factor-clock}E Gxdpll5_m2_d4_ckfixed-factor-clock}sGydpll5_m2_d8_ckfixed-factor-clock}sGzdpll5_m2_d16_ckfixed-factor-clock}sG{dpll5_m2_d20_ckfixed-factor-clock}sG|usim_mux_fck@c40ti,composite-mux-clock(}tuvwxyz{|y @G~usim_fckti,composite-clock}}~usim_ick@c10ti,omap3-interface-clock}Ny  Gdpll5_ck@d04ti,omap3-dpll-clock}y  $ L 4sGdpll5_m2_ck@d50ti,divider-clock}y PGssgx_gate_fck@b00ti,composite-gate-clock}&y Gcore_d3_ckfixed-factor-clock}&Gcore_d4_ckfixed-factor-clock}&Gcore_d6_ckfixed-factor-clock}&Gomap_192m_alwon_fckfixed-factor-clock}"Gcore_d2_ckfixed-factor-clock}&Gsgx_mux_fck@b40ti,composite-mux-clock }*y @Gsgx_fckti,composite-clock}Gsgx_ick@b10ti,wait-gate-clock}>y Gcpefuse_fck@a08ti,gate-clock}y Gts_fck@a08ti,gate-clock}@y Gusbtll_fck@a08ti,wait-gate-clock}sy Gusbtll_ick@a18ti,omap3-interface-clock}Jy Gmmchs3_ick@a10ti,omap3-interface-clock}Jy Gmmchs3_fck@a00ti,wait-gate-clock}y Gdss1_alwon_fck_3430es2@e00ti,dss-gate-clock}yJGdss_ick_3430es2@e10ti,omap3-dss-interface-clock}?yGusbhost_120m_fck@1400ti,gate-clock}syGusbhost_48m_fck@1400ti,dss-gate-clock}0yGusbhost_ick@1410ti,omap3-dss-interface-clock}?yGclockdomainscore_l3_clkdmti,clockdomain}dpll3_clkdmti,clockdomain}dpll1_clkdmti,clockdomain}per_clkdmti,clockdomainh}emu_clkdmti,clockdomain}fdpll4_clkdmti,clockdomain}wkup_clkdmti,clockdomain$}dss_clkdmti,clockdomain}core_l4_clkdmti,clockdomain}cam_clkdmti,clockdomain}iva2_clkdmti,clockdomain}dpll2_clkdmti,clockdomain}md2d_clkdmti,clockdomain }dpll5_clkdmti,clockdomain}sgx_clkdmti,clockdomain}usbhost_clkdmti,clockdomain }counter@48320000ti,omap-counter32kyH2  counter_32kinterrupt-controller@48200000ti,omap3-intcyH Gdma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmayH`  `dmaGgpio@48310000ti,omap3-gpioyH1gpio1gpio@49050000ti,omap3-gpioyIgpio2Ggpio@49052000ti,omap3-gpioyI gpio3gpio@49054000ti,omap3-gpioyI@ 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Gregulator-vdacti,twl4030-vdacyw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1y:0Gregulator-vmmc2ti,twl4030-vmmc2y:0regulator-vusb1v5ti,twl4030-vusb1v5Gregulator-vusb1v8ti,twl4030-vusb1v8Gregulator-vusb3v1ti,twl4030-vusb3v1Gregulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2yw@w@gregulator-vsimti,twl4030-vsimyw@-gpioti,twl4030-gpioGtwl4030-usbti,twl4030-usb {Gpwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypadD?  @A Bsrmadcti,twl4030-madcGi2c@48072000 ti,omap3-i2cyH 9txrx+i2c2i2c@48060000 ti,omap3-i2cyH=txrx+i2c3mailbox@48094000ti,omap3-mailboxmailboxyH @$dsp 6 Aspi@48098000ti,omap2-mcspiyH A+mcspi1L@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3tsc2046@0y ti,tsc2046ZB@lw@(  spi@4809a000ti,omap2-mcspiyH B+mcspi2L +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiyH [+mcspi3L tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiyH 0+mcspi4LFGtx0rx01w@480b2000 ti,omap3-1wyH :hdq1wmmc@4809c000ti,omap3-pre-es3-hsmmcyH Smmc1=>txrxdefault"mmc@480b4000ti,omap3-hsmmcyH @Vmmc2/0txrx disabledmmc@480ad000ti,omap3-hsmmcyH ^mmc3MNtxrx disabledmmu@480bd400ti,omap2-iommuyH mmu_isp%Gmmu@5d000000ti,omap2-iommuy]mmu_iva disabledwdt@48314000 ti,omap3-wdtyH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspyH@5mpu ;< ?commontxrxOmcbsp1 txrx}fck disabledmcbsp@49022000ti,omap3-mcbspyI I 5mpusidetone>??commontxrxsidetoneOmcbsp2mcbsp2_sidetone!"txrx}fckick disabledmcbsp@49024000ti,omap3-mcbspyI@I 5mpusidetoneYZ?commontxrxsidetoneOmcbsp3mcbsp3_sidetonetxrx}fckick disabledmcbsp@49026000ti,omap3-mcbspyI`5mpu 67 ?commontxrxOmcbsp4txrx}fck^ disabledmcbsp@48096000ti,omap3-mcbspyH `5mpu QR ?commontxrxOmcbsp5txrx}fck disabledsham@480c3000ti,omap3-shamshamyH 0d1Erxtimer@48318000ti,omap3430-timeryH1%timer1otimer@49032000ti,omap3430-timeryI &timer2timer@49034000ti,omap3430-timeryI@'timer3timer@49036000ti,omap3430-timeryI`(timer4timer@49038000ti,omap3430-timeryI)timer5~timer@4903a000ti,omap3430-timeryI*timer6~timer@4903c000ti,omap3430-timeryI+timer7~timer@4903e000ti,omap3430-timeryI,timer8~timer@49040000ti,omap3430-timeryI-timer9timer@48086000ti,omap3430-timeryH`.timer10timer@48088000ti,omap3430-timeryH/timer11timer@48304000ti,omap3430-timeryH0@_timer12ousbhstll@48062000 ti,usbhs-tllyH N usb_tll_hsusbhshost@48064000ti,usbhs-hostyH@ usb_host_hs+ohci@48064400ti,ohci-omap3yHDLehci@48064800 ti,ehci-omapyHHMgpmc@6e000000ti,omap3430-gpmcgpmcynrxtx+ 0Gethernet@gpmcsmsc,lan9221smsc,lan9115/=Oap(--xK2KLd{  ynand@0,0ti,omap2-nand y  micron,nandbch8/=,O,ap",(6@RR({+partition@0 %X-Loaderypartition@80000%U-Bootypartition@1c0000 %Environmentypartition@200000%Kernely partition@2000000 %Filesystemyusb_otg_hs@480ab000ti,omap3-musbyH \]?mcdma usb_otg_hs+6> default"GV^2dss@48050000 ti,omap3-dssyHok dss_core}fck+dispc@48050400ti,omap3-dispcyH dss_dispc}fckencoder@4804fc00 ti,omap3-dsiyHH@H 5protophypll disabled dss_dsi1} fcksys_clkencoder@48050800ti,omap3-rfbiyH disabled dss_rfbi}fckickencoder@48050c00ti,omap3-vencyH  disabled dss_venc}fckportendpointdtGssi-controller@48058000 ti,omap3-ssissiokyHH5sysgddG?gdd_mpu+ }q ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portyHH5txrxCDssi-port@4805b000ti,omap3-ssi-portyHH5txrxEFpinmux@480025d8 ti,omap3-padconfpinctrl-singleyH%$+ *isp@480bc000 ti,omap3-ispyH H |clports+bandgap@48002524yH%$ti,omap34xx-bandgapGtarget-module@480cb000ti,sysc-omap3430-srti,syscsmartreflex_coreyH $5sysc}fck+ H smartreflex@0ti,omap3-smartreflex-coreytarget-module@480c9000ti,sysc-omap3430-srti,syscsmartreflex_mpu_ivayH $5sysc}fck+ H smartreflex@480c9000ti,omap3-smartreflex-mpu-ivaytarget-module@50000000ti,sysc-omap2ti,syscyP5rev}fckick+ P@thermal-zonescpu_thermalN regulator-vddvarioregulator-fixed jvddvariogGregulator-vdd33aregulator-fixedjvdd33agGmemory@80000000mmemoryygpio_keys gpio-keysdefault"key_enter%enter key_f1%f1 ;key_f2%f2 <key_f3%f3 =key_f4%f4  >key_left%left  ikey_right%right  jkey_up%up  gkey_down%down  lbacklightgpio-backlight  regulator-lcd-3v3regulator-fixedjlcd_3v3y2Z2Z pgGdisplaysharp,ls037v7dw01%lcd # 0 = J VportendpointdG compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-pointscpu0-supplyinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskphandlepinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0ti,use_poweroffbci3v1-supplyio-channelsio-channel-namesregulator-always-onusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencyvcc-supplyti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,swap-xywakeup-sourcependown-gpioti,dual-voltpbias-supplyvmmc-supplybus-widthstatus#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-size#sound-dai-cellsti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureremote-wakeup-connectedgpmc,num-csgpmc,num-waitpinsbank-widthgpmc,device-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsgpmc,wr-data-mux-bus-nsgpmc,wr-access-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addresslinux,mtd-namenand-bus-widthti,nand-ecc-optgpmc,sync-clk-pslabelmultipointnum-epsram-bitsinterface-typeusb-phypowerremote-endpointdata-linesiommusti,phy-type#thermal-sensor-cellsti,sysc-maskpolling-delay-passivepolling-delaycoefficientsthermal-sensorsgpioslinux,codedefault-onstartup-delay-uspower-supplyenvdd-supplyenable-gpiosreset-gpiosmode-gpios