D8p( 8Hgumstix,omap3-overo-chestnut43gumstix,omap3-overoti,omap36xxti,omap3 +37OMAP36xx/AM37xx/DM37xx Gumstix Overo on Chestnut43chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000d/ocp@68000000/serial@49042000 l/displaycpus+cpu@0arm,cortex-a8ucpucpus 'O 57pmu@54000000arm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bush +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus + pinmux@30 ti,omap3-padconfpinctrl-single08+&CdefaultQ[pinmux_uart2_pins c<>@B[pinmux_i2c1_pinsc[pinmux_mmc1_pins0c[pinmux_mmc2_pins0c(*,.02[pinmux_w3cbw003c_pinscl[pinmux_hsusb2_pins@c      [pinmux_twl4030_pinscA[pinmux_i2c3_pinsc[pinmux_uart3_pinscnp[pinmux_dss_dpi_pinsc[pinmux_lte430_pinscD[pinmux_backlight_pinscF[pinmux_mcspi1_pins c[pinmux_ads7846_pinsc [scm_conf@270sysconsimple-busp0+ p0[pbias_regulator@2b0ti,pbias-omap3ti,pbias-omapwpbias_mmc_omap2430~pbias_mmc_omap2430w@-[clocks+mcbsp5_mux_fck@68ti,composite-mux-clockh[mcbsp5_fckti,composite-clock[mcbsp1_mux_fck@4ti,composite-mux-clock[ mcbsp1_fckti,composite-clock [mcbsp2_mux_fck@4ti,composite-mux-clock [ mcbsp2_fckti,composite-clock [mcbsp3_mux_fck@68ti,composite-mux-clock h[mcbsp3_fckti,composite-clock[mcbsp4_mux_fck@68ti,composite-mux-clock h[mcbsp4_fckti,composite-clock[clockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \+&pinmux_twl4030_vpins c[aes@480c5000 ti,omap3-aesaesH PPABtxrxprm@48306000 ti,omap3-prmH0`@ clocks+virt_16_8m_ck fixed-clockY[osc_sys_ck@d40 ti,mux-clock @[sys_ck@1270ti,divider-clockp[sys_clkout1@d70ti,gate-clock pdpll3_x2_ckfixed-factor-clock#dpll3_m2x2_ckfixed-factor-clock#[dpll4_x2_ckfixed-factor-clock#corex2_fckfixed-factor-clock#[wkup_l4_ickfixed-factor-clock#[Ncorex2_d3_fckfixed-factor-clock#[corex2_d5_fckfixed-factor-clock#[clockdomainscm@48004000 ti,omap3-cmH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clock[@virt_12m_ck fixed-clock[virt_13m_ck fixed-clock]@[virt_19200000_ck fixed-clock$[virt_26000000_ck fixed-clock[virt_38_4m_ck fixed-clockI[dpll4_ck@d00ti,omap3-dpll-per-j-type-clock D 0[dpll4_m2_ck@d48ti,divider-clock? H[ dpll4_m2x2_mul_ckfixed-factor-clock #[!dpll4_m2x2_ck@d00ti,hsdiv-gate-clock! -["omap_96m_alwon_fckfixed-factor-clock"#[)dpll3_ck@d00ti,omap3-dpll-core-clock @ 0[dpll3_m3_ck@1140ti,divider-clock@[#dpll3_m3x2_mul_ckfixed-factor-clock##[$dpll3_m3x2_ck@d00ti,hsdiv-gate-clock$  -[%emu_core_alwon_ckfixed-factor-clock%#[bsys_altclk fixed-clock[.mcbsp_clks fixed-clock[dpll3_m2_ck@d40ti,divider-clock @[core_ckfixed-factor-clock#[&dpll1_fck@940ti,divider-clock& @['dpll1_ck@904ti,omap3-dpll-clock'  $ @ 4[dpll1_x2_ckfixed-factor-clock#[(dpll1_x2m2_ck@944ti,divider-clock( D[<cm_96m_fckfixed-factor-clock)#[*omap_96m_fck@d40 ti,mux-clock* @[Edpll4_m3_ck@e40ti,divider-clock @[+dpll4_m3x2_mul_ckfixed-factor-clock+#[,dpll4_m3x2_ck@d00ti,hsdiv-gate-clock, -[-omap_54m_fck@d40 ti,mux-clock-. @[8cm_96m_d2_fckfixed-factor-clock*#[/omap_48m_fck@d40 ti,mux-clock/. @[0omap_12m_fckfixed-factor-clock0#[Gdpll4_m4_ck@e40ti,divider-clock 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des1_ick@a14ti,omap3-interface-clocki cam_mclk@f00ti,gate-clockj^cam_ick@f10!ti,omap3-no-wait-interface-clock?[csi2_96m_fck@f00ti,gate-clock[security_l3_ickfixed-factor-clock>#[kpka_ick@a14ti,omap3-interface-clockk icr_ick@a10ti,omap3-interface-clockJ des2_ick@a10ti,omap3-interface-clockJ mspro_ick@a10ti,omap3-interface-clockJ mailboxes_ick@a10ti,omap3-interface-clockJ ssi_l4_ickfixed-factor-clock?#[rsr1_fck@c00ti,wait-gate-clock [ sr2_fck@c00ti,wait-gate-clock [ sr_l4_ickfixed-factor-clock?#dpll2_fck@40ti,divider-clock&@[ldpll2_ck@4ti,omap3-dpll-clockl$@4[mdpll2_m2_ck@44ti,divider-clockmD[niva2_ck@0ti,wait-gate-clockn[modem_fck@a00ti,omap3-interface-clock [sad2d_ick@a10ti,omap3-interface-clock> [mad2d_ick@a18ti,omap3-interface-clock> [mspro_fck@a00ti,wait-gate-clock ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock [ossi_ssr_div_fck_3430es2@a40ti,composite-divider-clock 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&timer2timer@49034000ti,omap3430-timerI@'timer3timer@49036000ti,omap3430-timerI`(timer4timer@49038000ti,omap3430-timerI)timer5timer@4903a000ti,omap3430-timerI*timer6timer@4903c000ti,omap3430-timerI+timer7timer@4903e000ti,omap3430-timerI,timer8timer@49040000ti,omap3430-timerI-timer9timer@48086000ti,omap3430-timerH`.timer10timer@48088000ti,omap3430-timerH/timer11timer@48304000ti,omap3430-timerH0@_timer12usbhstll@48062000 ti,usbhs-tllH N usb_tll_hsusbhshost@48064000ti,usbhs-hostH@ usb_host_hs+ ehci-phyohci@48064400ti,ohci-omap3HDLehci@48064800 ti,ehci-omapHHM1gpmc@6e000000ti,omap3430-gpmcgpmcnrxtx6B+00+,[nand@0,0ti,omap2-nandTmicron,mt29c4g96maz  crbch8,,", (6*@9RJR[(m+partition@0SPLpartition@80000U-Bootpartition@1c0000 Environment$partition@280000Kernel(partition@780000 Filesystemethernet@gpmcsmsc,lan9221smsc,lan9115*$  * $9<J6*$m[*  ) C S a n  usb_otg_hs@480ab000ti,omap3-musbH \]mcdma usb_otg_hs     1 usb2-phy 2dss@48050000 ti,omap3-dssHok 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~vddvarioS[regulator-vdd33aregulator-fixed~vdd33aS[ compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2serial3display0device_typeregclocksclock-namesclock-latencyoperating-pointsinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0phandlepinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyio-channelsio-channel-namesregulator-always-onti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cellsstatuspagesizeVdd-supplyVdd_IO-supplyst,click-single-xst,click-single-yst,click-single-zst,click-thresh-xst,click-thresh-yst,click-thresh-zst,irq1-clickst,irq2-clickst,wakeup-x-lost,wakeup-x-hist,wakeup-y-lost,wakeup-y-hist,wakeup-z-lost,wakeup-z-hist,min-limit-xst,min-limit-yst,min-limit-zst,max-limit-xst,max-limit-yst,max-limit-z#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csvcc-supplyspi-max-frequencypendown-gpioti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxwakeup-sourceti,dual-voltpbias-supplyvmmc-supplybus-widthvqmmc-supplycap-sdio-irqnon-removable#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-size#sound-dai-cellsti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinslinux,mtd-namenand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelbank-widthgpmc,mux-add-datagpmc,oe-on-nsgpmc,we-on-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsenvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerremote-endpointdata-linesti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-type#thermal-sensor-cellsti,sysc-maskti,sysc-sidleti,sysc-midlepolling-delay-passivepolling-delaycoefficientsthermal-sensorspwmsmax-brightnesslinux,default-triggerti,modelti,mcbspstartup-delay-usenable-active-highreset-gpiosenable-gpioshactivevactivehfront-porchhback-porchhsync-lenvback-porchvfront-porchvsync-lenhsync-activevsync-activede-activepixelclk-activedefault-onlinux,code