8(( Fcompulab,omap3-sbc-t3530compulab,omap3-cm-t3530ti,omap34xxti,omap3 +!7CompuLab SBC-T3530 with CM-T3530chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000d/dvi-connectorm/svideo-connectorcpus+cpu@0arm,cortex-a8vcpucpu(HАg8 Odp` 'ppmu@54000000arm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bush +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus + pinmux@30 ti,omap3-padconfpinctrl-single08+3Pdefault^pinmux_uart3_pinshnp|pinmux_mmc1_pins0h|pinmux_green_led_pinsh|pinmux_dss_dpi_pins_commonh|pinmux_dss_dpi_pins_cm_t35x0h| pinmux_ads7846_pinsh|pinmux_mcspi1_pins h|pinmux_i2c1_pinsh|pinmux_mcbsp2_pins h |pinmux_smsc1_pinshj|pinmux_hsusb0_pins`hrtvxz|~|pinmux_twl4030_pinshA|pinmux_mmc2_pinsPh(*,.02468:|pinmux_smsc2_pinsh|pinmux_tfp410_pinsh|pinmux_i2c3_pinsh|pinmux_sb_t35_audio_amph|pinmux_sb_t35_usb_hub_pinsh|scm_conf@270sysconsimple-busp0+ p0|pbias_regulator@2b0ti,pbias-omap3ti,pbias-omappbias_mmc_omap2430pbias_mmc_omap2430w@-|clocks+mcbsp5_mux_fck@68ti,composite-mux-clockh| mcbsp5_fckti,composite-clock |mcbsp1_mux_fck@4ti,composite-mux-clock| mcbsp1_fckti,composite-clock |mcbsp2_mux_fck@4ti,composite-mux-clock |mcbsp2_fckti,composite-clock |mcbsp3_mux_fck@68ti,composite-mux-clock h|mcbsp3_fckti,composite-clock|mcbsp4_mux_fck@68ti,composite-mux-clock h|mcbsp4_fckti,composite-clock|clockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \+3pinmux_twl4030_vpins h|aes@480c5000 ti,omap3-aesaesH PPABtxrxprm@48306000 ti,omap3-prmH0`@ clocks+virt_16_8m_ck fixed-clockY|osc_sys_ck@d40 ti,mux-clock @|sys_ck@1270ti,divider-clockp|sys_clkout1@d70ti,gate-clock pdpll3_x2_ckfixed-factor-clock%0dpll3_m2x2_ckfixed-factor-clock%0|dpll4_x2_ckfixed-factor-clock%0corex2_fckfixed-factor-clock%0| wkup_l4_ickfixed-factor-clock%0|Ocorex2_d3_fckfixed-factor-clock %0|corex2_d5_fckfixed-factor-clock %0|clockdomainscm@48004000 ti,omap3-cmH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clock|Avirt_12m_ck fixed-clock|virt_13m_ck fixed-clock]@|virt_19200000_ck fixed-clock$|virt_26000000_ck fixed-clock|virt_38_4m_ck fixed-clockI|dpll4_ck@d00ti,omap3-dpll-per-clock D 0|dpll4_m2_ck@d48ti,divider-clock? H|!dpll4_m2x2_mul_ckfixed-factor-clock!%0|"dpll4_m2x2_ck@d00ti,gate-clock" :|#omap_96m_alwon_fckfixed-factor-clock#%0|*dpll3_ck@d00ti,omap3-dpll-core-clock @ 0|dpll3_m3_ck@1140ti,divider-clock@|$dpll3_m3x2_mul_ckfixed-factor-clock$%0|%dpll3_m3x2_ck@d00ti,gate-clock%  :|&emu_core_alwon_ckfixed-factor-clock&%0|csys_altclk fixed-clock|/mcbsp_clks fixed-clock|dpll3_m2_ck@d40ti,divider-clock @|core_ckfixed-factor-clock%0|'dpll1_fck@940ti,divider-clock' @|(dpll1_ck@904ti,omap3-dpll-clock(  $ @ 4|dpll1_x2_ckfixed-factor-clock%0|)dpll1_x2m2_ck@944ti,divider-clock) D|=cm_96m_fckfixed-factor-clock*%0|+omap_96m_fck@d40 ti,mux-clock+ @|Fdpll4_m3_ck@e40ti,divider-clock @|,dpll4_m3x2_mul_ckfixed-factor-clock,%0|-dpll4_m3x2_ck@d00ti,gate-clock- :|.omap_54m_fck@d40 ti,mux-clock./ @|9cm_96m_d2_fckfixed-factor-clock+%0|0omap_48m_fck@d40 ti,mux-clock0/ @|1omap_12m_fckfixed-factor-clock1%0|Hdpll4_m4_ck@e40ti,divider-clock @|2dpll4_m4x2_mul_ckti,fixed-factor-clock2P^k|3dpll4_m4x2_ck@d00ti,gate-clock3 :k|dpll4_m5_ck@f40ti,divider-clock?@|4dpll4_m5x2_mul_ckti,fixed-factor-clock4P^k|5dpll4_m5x2_ck@d00ti,gate-clock5 :k|kdpll4_m6_ck@1140ti,divider-clock?@|6dpll4_m6x2_mul_ckfixed-factor-clock6%0|7dpll4_m6x2_ck@d00ti,gate-clock7 :|8emu_per_alwon_ckfixed-factor-clock8%0|dclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock' p|:clkout2_src_mux_ck@d70ti,composite-mux-clock'+9 p|;clkout2_src_ckti,composite-clock:;|<sys_clkout2@d70ti,divider-clock<@ p~mpu_ckfixed-factor-clock=%0|>arm_fck@924ti,divider-clock> $emu_mpu_alwon_ckfixed-factor-clock>%0|el3_ick@a40ti,divider-clock' @|?l4_ick@a40ti,divider-clock? @|@rm_ick@c40ti,divider-clock@ @gpt10_gate_fck@a00ti,composite-gate-clock  |Bgpt10_mux_fck@a40ti,composite-mux-clockA @|Cgpt10_fckti,composite-clockBCgpt11_gate_fck@a00ti,composite-gate-clock  |Dgpt11_mux_fck@a40ti,composite-mux-clockA @|Egpt11_fckti,composite-clockDEcore_96m_fckfixed-factor-clockF%0|mmchs2_fck@a00ti,wait-gate-clock |mmchs1_fck@a00ti,wait-gate-clock |i2c3_fck@a00ti,wait-gate-clock |i2c2_fck@a00ti,wait-gate-clock |i2c1_fck@a00ti,wait-gate-clock |mcbsp5_gate_fck@a00ti,composite-gate-clock  |mcbsp1_gate_fck@a00ti,composite-gate-clock  | core_48m_fckfixed-factor-clock1%0|Gmcspi4_fck@a00ti,wait-gate-clockG |mcspi3_fck@a00ti,wait-gate-clockG |mcspi2_fck@a00ti,wait-gate-clockG |mcspi1_fck@a00ti,wait-gate-clockG |uart2_fck@a00ti,wait-gate-clockG |uart1_fck@a00ti,wait-gate-clockG  |core_12m_fckfixed-factor-clockH%0|Ihdq_fck@a00ti,wait-gate-clockI |core_l3_ickfixed-factor-clock?%0|Jsdrc_ick@a10ti,wait-gate-clockJ |gpmc_fckfixed-factor-clockJ%0core_l4_ickfixed-factor-clock@%0|Kmmchs2_ick@a10ti,omap3-interface-clockK |mmchs1_ick@a10ti,omap3-interface-clockK |hdq_ick@a10ti,omap3-interface-clockK |mcspi4_ick@a10ti,omap3-interface-clockK |mcspi3_ick@a10ti,omap3-interface-clockK |mcspi2_ick@a10ti,omap3-interface-clockK |mcspi1_ick@a10ti,omap3-interface-clockK |i2c3_ick@a10ti,omap3-interface-clockK |i2c2_ick@a10ti,omap3-interface-clockK |i2c1_ick@a10ti,omap3-interface-clockK |uart2_ick@a10ti,omap3-interface-clockK |uart1_ick@a10ti,omap3-interface-clockK  |gpt11_ick@a10ti,omap3-interface-clockK  |gpt10_ick@a10ti,omap3-interface-clockK  |mcbsp5_ick@a10ti,omap3-interface-clockK  |mcbsp1_ick@a10ti,omap3-interface-clockK  |omapctrl_ick@a10ti,omap3-interface-clockK |dss_tv_fck@e00ti,gate-clock9|dss_96m_fck@e00ti,gate-clockF|dss2_alwon_fck@e00ti,gate-clock|dummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock |Lgpt1_mux_fck@c40ti,composite-mux-clockA @|Mgpt1_fckti,composite-clockLMaes2_ick@a10ti,omap3-interface-clockK |wkup_32k_fckfixed-factor-clockA%0|Ngpio1_dbck@c00ti,gate-clockN |sha12_ick@a10ti,omap3-interface-clockK |wdt2_fck@c00ti,wait-gate-clockN |wdt2_ick@c10ti,omap3-interface-clockO |wdt1_ick@c10ti,omap3-interface-clockO |gpio1_ick@c10ti,omap3-interface-clockO |omap_32ksync_ick@c10ti,omap3-interface-clockO |gpt12_ick@c10ti,omap3-interface-clockO |gpt1_ick@c10ti,omap3-interface-clockO |per_96m_fckfixed-factor-clock*%0| per_48m_fckfixed-factor-clock1%0|Puart3_fck@1000ti,wait-gate-clockP |gpt2_gate_fck@1000ti,composite-gate-clock|Qgpt2_mux_fck@1040ti,composite-mux-clockA@|Rgpt2_fckti,composite-clockQRgpt3_gate_fck@1000ti,composite-gate-clock|Sgpt3_mux_fck@1040ti,composite-mux-clockA@|Tgpt3_fckti,composite-clockSTgpt4_gate_fck@1000ti,composite-gate-clock|Ugpt4_mux_fck@1040ti,composite-mux-clockA@|Vgpt4_fckti,composite-clockUVgpt5_gate_fck@1000ti,composite-gate-clock|Wgpt5_mux_fck@1040ti,composite-mux-clockA@|Xgpt5_fckti,composite-clockWXgpt6_gate_fck@1000ti,composite-gate-clock|Ygpt6_mux_fck@1040ti,composite-mux-clockA@|Zgpt6_fckti,composite-clockYZgpt7_gate_fck@1000ti,composite-gate-clock|[gpt7_mux_fck@1040ti,composite-mux-clockA@|\gpt7_fckti,composite-clock[\gpt8_gate_fck@1000ti,composite-gate-clock |]gpt8_mux_fck@1040ti,composite-mux-clockA@|^gpt8_fckti,composite-clock]^gpt9_gate_fck@1000ti,composite-gate-clock |_gpt9_mux_fck@1040ti,composite-mux-clockA@|`gpt9_fckti,composite-clock_`per_32k_alwon_fckfixed-factor-clockA%0|agpio6_dbck@1000ti,gate-clocka|gpio5_dbck@1000ti,gate-clocka|gpio4_dbck@1000ti,gate-clocka|gpio3_dbck@1000ti,gate-clocka|gpio2_dbck@1000ti,gate-clocka |wdt3_fck@1000ti,wait-gate-clocka |per_l4_ickfixed-factor-clock@%0|bgpio6_ick@1010ti,omap3-interface-clockb|gpio5_ick@1010ti,omap3-interface-clockb|gpio4_ick@1010ti,omap3-interface-clockb|gpio3_ick@1010ti,omap3-interface-clockb|gpio2_ick@1010ti,omap3-interface-clockb |wdt3_ick@1010ti,omap3-interface-clockb |uart3_ick@1010ti,omap3-interface-clockb |uart4_ick@1010ti,omap3-interface-clockb|gpt9_ick@1010ti,omap3-interface-clockb |gpt8_ick@1010ti,omap3-interface-clockb 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des1_ick@a14ti,omap3-interface-clockj cam_mclk@f00ti,gate-clockkkcam_ick@f10!ti,omap3-no-wait-interface-clock@|csi2_96m_fck@f00ti,gate-clock|security_l3_ickfixed-factor-clock?%0|lpka_ick@a14ti,omap3-interface-clockl icr_ick@a10ti,omap3-interface-clockK des2_ick@a10ti,omap3-interface-clockK mspro_ick@a10ti,omap3-interface-clockK mailboxes_ick@a10ti,omap3-interface-clockK ssi_l4_ickfixed-factor-clock@%0|ssr1_fck@c00ti,wait-gate-clock |sr2_fck@c00ti,wait-gate-clock |sr_l4_ickfixed-factor-clock@%0dpll2_fck@40ti,divider-clock'@|mdpll2_ck@4ti,omap3-dpll-clockm$@4|ndpll2_m2_ck@44ti,divider-clocknD|oiva2_ck@0ti,wait-gate-clocko|modem_fck@a00ti,omap3-interface-clock |sad2d_ick@a10ti,omap3-interface-clock? |mad2d_ick@a18ti,omap3-interface-clock? |mspro_fck@a00ti,wait-gate-clock ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock  |pssi_ssr_div_fck_3430es2@a40ti,composite-divider-clock  @$|qssi_ssr_fck_3430es2ti,composite-clockpq|rssi_sst_fck_3430es2fixed-factor-clockr%0| hsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clockJ |ssi_ick_3430es2@a10ti,omap3-ssi-interface-clocks |usim_gate_fck@c00ti,composite-gate-clockF  |~sys_d2_ckfixed-factor-clock%0|uomap_96m_d2_fckfixed-factor-clockF%0|vomap_96m_d4_fckfixed-factor-clockF%0|womap_96m_d8_fckfixed-factor-clockF%0|xomap_96m_d10_fckfixed-factor-clockF%0 |ydpll5_m2_d4_ckfixed-factor-clockt%0|zdpll5_m2_d8_ckfixed-factor-clockt%0|{dpll5_m2_d16_ckfixed-factor-clockt%0||dpll5_m2_d20_ckfixed-factor-clockt%0|}usim_mux_fck@c40ti,composite-mux-clock(uvwxyz{|} @|usim_fckti,composite-clock~usim_ick@c10ti,omap3-interface-clockO  |dpll5_ck@d04ti,omap3-dpll-clock  $ L 4|dpll5_m2_ck@d50ti,divider-clock P|tsgx_gate_fck@b00ti,composite-gate-clock' |core_d3_ckfixed-factor-clock'%0|core_d4_ckfixed-factor-clock'%0|core_d6_ckfixed-factor-clock'%0|omap_192m_alwon_fckfixed-factor-clock#%0|core_d2_ckfixed-factor-clock'%0|sgx_mux_fck@b40ti,composite-mux-clock + @|sgx_fckti,composite-clock|sgx_ick@b10ti,wait-gate-clock? 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ti,omap3-dssHeok dss_corefck+Pdefault^ dispc@48050400ti,omap3-dispcH dss_dispcfckencoder@4804fc00 ti,omap3-dsiHH@H protophypll edisabled dss_dsi1 fcksys_clkencoder@48050800ti,omap3-rfbiH edisabled dss_rfbifckickencoder@48050c00ti,omap3-vencH eok dss_vencfck portendpoint |portendpoint |ssi-controller@48058000 ti,omap3-ssissieokHHsysgddGgdd_mpu+ r  ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portHHtxrxCDssi-port@4805b000ti,omap3-ssi-portHHtxrxEFpinmux@480025d8 ti,omap3-padconfpinctrl-singleH%$+3isp@480bc000 ti,omap3-ispH H |lports+bandgap@48002524H%$ti,omap34xx-bandgap |target-module@480cb000ti,sysc-omap3430-srti,syscsmartreflex_coreH $sysc fck+ H smartreflex@0ti,omap3-smartreflex-coretarget-module@480c9000ti,sysc-omap3430-srti,syscsmartreflex_mpu_ivaH $sysc fck+ H smartreflex@480c9000ti,omap3-smartreflex-mpu-ivatarget-module@50000000ti,sysc-omap2ti,syscPrevfckick+ P@thermal-zonescpu_thermal & < JN  Wmemory@80000000vmemoryleds gpio-ledsPdefault^ledb cm-t3x:green > gheartbeathsusb1_power_regregulator-fixed hsusb1_vbus2Z2Z }p|hsusb2_power_regregulator-fixed hsusb2_vbus2Z2Z }p|hsusb1_phyusb-nop-xceiv_ |hsusb2_phyusb-nop-xceiv_ |ads7846-regregulator-fixed ads7846-reg2Z2Z|svideo-connectorsvideo-connectortvportendpoint| soundti,omap-twl4030 cm-t35 regulator-vddvarioregulator-fixed vddvario |regulator-vdd33aregulator-fixedvdd33a |regulator-mmc2-sdio-resetregulator-fixedregulator-mmc2-sdio-reset2Z2Z  |encoder ti,tfp410 Pdefault^ports+port@0endpoint| port@1endpoint|dvi-connectordvi-connectordviportendpoint|audio_ampregulator-fixed audio_ampPdefault^   compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2display0display1device_typeregclocksclock-namesclock-latencyoperating-pointscpu0-supplyinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinsphandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpagesizebci3v1-supplyio-channelsio-channel-namesti,use-ledsti,pullupsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csvcc-supplyspi-max-frequencypendown-gpioti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,debounce-maxti,debounce-tolti,debounce-repwakeup-sourceti,dual-voltpbias-supplybus-widthvmmc-supplycd-gpiosnon-removablecap-power-off-cardstatus#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-size#sound-dai-cellsti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport1-modeport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,page-burst-access-nsgpmc,access-nsgpmc,cycle2cycle-delay-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelbank-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,bus-turnaround-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowervdda-supplyremote-endpointti,channelsdata-linesiommusti,phy-type#thermal-sensor-cellsti,sysc-maskpolling-delay-passivepolling-delaycoefficientsthermal-sensorslinux,default-triggerstartup-delay-usreset-gpiosti,modelti,mcbspregulator-always-onenable-active-highpowerdown-gpios