8`((Gtechnexion,omap3-thundertechnexion,omap3-tao3530ti,omap34xxti,omap3 +,7TI OMAP3 Thunder baseboard with TAO3530 SOMchosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000 d/displaycpus+cpu@0arm,cortex-a8mcpuy}cpu(HАg8 Odp` 'ppmu@54000000arm,cortex-a8-pmuyTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busyh +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-busy + pinmux@30 ti,omap3-padconfpinctrl-singley08+ *pinmux_hsusbb2_pins`G          pinmux_mmc1_pinsPG "$&[pinmux_mmc2_pins0G(*,.02[pinmux_wlan_gpioG^pinmux_uart3_pinsGnAp[pinmux_i2c3_pinsG[pinmux_mcspi1_pins G[pinmux_mcspi3_pins G[pinmux_mcbsp3_pins G<>@B[pinmux_twl4030_pinsGA[pinmux_dss_dpi_pinsG[pinmux_lte430_pinsG8[ pinmux_backlight_pinsG:[ scm_conf@270sysconsimple-busyp0+ p0[pbias_regulator@2b0ti,pbias-omap3ti,pbias-omapycpbias_mmc_omap2430jpbias_mmc_omap2430yw@-[clocks+mcbsp5_mux_fck@68ti,composite-mux-clock}yh[mcbsp5_fckti,composite-clock}[mcbsp1_mux_fck@4ti,composite-mux-clock}y[ mcbsp1_fckti,composite-clock} [mcbsp2_mux_fck@4ti,composite-mux-clock} y[ mcbsp2_fckti,composite-clock} [mcbsp3_mux_fck@68ti,composite-mux-clock} yh[mcbsp3_fckti,composite-clock}[mcbsp4_mux_fck@68ti,composite-mux-clock} yh[mcbsp4_fckti,composite-clock}[clockdomainspinmux@a00 ti,omap3-padconfpinctrl-singley \+ *pinmux_twl4030_vpins G[aes@480c5000 ti,omap3-aesaesyH PPABtxrx disabledprm@48306000 ti,omap3-prmyH0`@ clocks+virt_16_8m_ck fixed-clockY[osc_sys_ck@d40 ti,mux-clock}y @[sys_ck@1270ti,divider-clock}yp[sys_clkout1@d70ti,gate-clock}y pdpll3_x2_ckfixed-factor-clock} dpll3_m2x2_ckfixed-factor-clock} [dpll4_x2_ckfixed-factor-clock} corex2_fckfixed-factor-clock} [wkup_l4_ickfixed-factor-clock} [Ncorex2_d3_fckfixed-factor-clock} [corex2_d5_fckfixed-factor-clock} [clockdomainscm@48004000 ti,omap3-cmyH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clock[@virt_12m_ck fixed-clock[virt_13m_ck fixed-clock]@[virt_19200000_ck fixed-clock$[virt_26000000_ck fixed-clock[virt_38_4m_ck fixed-clockI[dpll4_ck@d00ti,omap3-dpll-per-clock}y D 0[dpll4_m2_ck@d48ti,divider-clock}?y H[ dpll4_m2x2_mul_ckfixed-factor-clock}  [!dpll4_m2x2_ck@d00ti,gate-clock}!y  ["omap_96m_alwon_fckfixed-factor-clock}" [)dpll3_ck@d00ti,omap3-dpll-core-clock}y @ 0[dpll3_m3_ck@1140ti,divider-clock}y@[#dpll3_m3x2_mul_ckfixed-factor-clock}# [$dpll3_m3x2_ck@d00ti,gate-clock}$ y  [%emu_core_alwon_ckfixed-factor-clock}% [bsys_altclk fixed-clock[.mcbsp_clks fixed-clock[dpll3_m2_ck@d40ti,divider-clock}y @[core_ckfixed-factor-clock} [&dpll1_fck@940ti,divider-clock}&y @['dpll1_ck@904ti,omap3-dpll-clock}'y  $ @ 4[dpll1_x2_ckfixed-factor-clock} [(dpll1_x2m2_ck@944ti,divider-clock}(y D[<cm_96m_fckfixed-factor-clock}) [*omap_96m_fck@d40 ti,mux-clock}*y @[Edpll4_m3_ck@e40ti,divider-clock} y@[+dpll4_m3x2_mul_ckfixed-factor-clock}+ [,dpll4_m3x2_ck@d00ti,gate-clock},y  [-omap_54m_fck@d40 ti,mux-clock}-.y @[8cm_96m_d2_fckfixed-factor-clock}* [/omap_48m_fck@d40 ti,mux-clock}/.y @[0omap_12m_fckfixed-factor-clock}0 [Gdpll4_m4_ck@e40ti,divider-clock} y@[1dpll4_m4x2_mul_ckti,fixed-factor-clock}16DQ[2dpll4_m4x2_ck@d00ti,gate-clock}2y  Q[dpll4_m5_ck@f40ti,divider-clock}?y@[3dpll4_m5x2_mul_ckti,fixed-factor-clock}36DQ[4dpll4_m5x2_ck@d00ti,gate-clock}4y  Q[jdpll4_m6_ck@1140ti,divider-clock}?y@[5dpll4_m6x2_mul_ckfixed-factor-clock}5 [6dpll4_m6x2_ck@d00ti,gate-clock}6y  [7emu_per_alwon_ckfixed-factor-clock}7 [cclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock}&y p[9clkout2_src_mux_ck@d70ti,composite-mux-clock}&*8y p[:clkout2_src_ckti,composite-clock}9:[;sys_clkout2@d70ti,divider-clock};@y pdmpu_ckfixed-factor-clock}< [=arm_fck@924ti,divider-clock}=y $emu_mpu_alwon_ckfixed-factor-clock}= [dl3_ick@a40ti,divider-clock}&y @[>l4_ick@a40ti,divider-clock}>y @[?rm_ick@c40ti,divider-clock}?y @gpt10_gate_fck@a00ti,composite-gate-clock} y [Agpt10_mux_fck@a40ti,composite-mux-clock}@y @[Bgpt10_fckti,composite-clock}ABgpt11_gate_fck@a00ti,composite-gate-clock} y [Cgpt11_mux_fck@a40ti,composite-mux-clock}@y @[Dgpt11_fckti,composite-clock}CDcore_96m_fckfixed-factor-clock}E [mmchs2_fck@a00ti,wait-gate-clock}y [mmchs1_fck@a00ti,wait-gate-clock}y [i2c3_fck@a00ti,wait-gate-clock}y [i2c2_fck@a00ti,wait-gate-clock}y [i2c1_fck@a00ti,wait-gate-clock}y [mcbsp5_gate_fck@a00ti,composite-gate-clock} y [mcbsp1_gate_fck@a00ti,composite-gate-clock} y [ core_48m_fckfixed-factor-clock}0 [Fmcspi4_fck@a00ti,wait-gate-clock}Fy [mcspi3_fck@a00ti,wait-gate-clock}Fy [mcspi2_fck@a00ti,wait-gate-clock}Fy [mcspi1_fck@a00ti,wait-gate-clock}Fy [uart2_fck@a00ti,wait-gate-clock}Fy [uart1_fck@a00ti,wait-gate-clock}Fy  [core_12m_fckfixed-factor-clock}G [Hhdq_fck@a00ti,wait-gate-clock}Hy [core_l3_ickfixed-factor-clock}> [Isdrc_ick@a10ti,wait-gate-clock}Iy [gpmc_fckfixed-factor-clock}I core_l4_ickfixed-factor-clock}? [Jmmchs2_ick@a10ti,omap3-interface-clock}Jy [mmchs1_ick@a10ti,omap3-interface-clock}Jy [hdq_ick@a10ti,omap3-interface-clock}Jy [mcspi4_ick@a10ti,omap3-interface-clock}Jy [mcspi3_ick@a10ti,omap3-interface-clock}Jy [mcspi2_ick@a10ti,omap3-interface-clock}Jy [mcspi1_ick@a10ti,omap3-interface-clock}Jy [i2c3_ick@a10ti,omap3-interface-clock}Jy [i2c2_ick@a10ti,omap3-interface-clock}Jy [i2c1_ick@a10ti,omap3-interface-clock}Jy [uart2_ick@a10ti,omap3-interface-clock}Jy [uart1_ick@a10ti,omap3-interface-clock}Jy  [gpt11_ick@a10ti,omap3-interface-clock}Jy  [gpt10_ick@a10ti,omap3-interface-clock}Jy  [mcbsp5_ick@a10ti,omap3-interface-clock}Jy  [mcbsp1_ick@a10ti,omap3-interface-clock}Jy  [omapctrl_ick@a10ti,omap3-interface-clock}Jy [dss_tv_fck@e00ti,gate-clock}8y[dss_96m_fck@e00ti,gate-clock}Ey[dss2_alwon_fck@e00ti,gate-clock}y[dummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock}y [Kgpt1_mux_fck@c40ti,composite-mux-clock}@y @[Lgpt1_fckti,composite-clock}KLaes2_ick@a10ti,omap3-interface-clock}Jy [wkup_32k_fckfixed-factor-clock}@ [Mgpio1_dbck@c00ti,gate-clock}My [sha12_ick@a10ti,omap3-interface-clock}Jy [wdt2_fck@c00ti,wait-gate-clock}My [wdt2_ick@c10ti,omap3-interface-clock}Ny [wdt1_ick@c10ti,omap3-interface-clock}Ny [gpio1_ick@c10ti,omap3-interface-clock}Ny [omap_32ksync_ick@c10ti,omap3-interface-clock}Ny [gpt12_ick@c10ti,omap3-interface-clock}Ny [gpt1_ick@c10ti,omap3-interface-clock}Ny [per_96m_fckfixed-factor-clock}) [ per_48m_fckfixed-factor-clock}0 [Ouart3_fck@1000ti,wait-gate-clock}Oy [gpt2_gate_fck@1000ti,composite-gate-clock}y[Pgpt2_mux_fck@1040ti,composite-mux-clock}@y@[Qgpt2_fckti,composite-clock}PQgpt3_gate_fck@1000ti,composite-gate-clock}y[Rgpt3_mux_fck@1040ti,composite-mux-clock}@y@[Sgpt3_fckti,composite-clock}RSgpt4_gate_fck@1000ti,composite-gate-clock}y[Tgpt4_mux_fck@1040ti,composite-mux-clock}@y@[Ugpt4_fckti,composite-clock}TUgpt5_gate_fck@1000ti,composite-gate-clock}y[Vgpt5_mux_fck@1040ti,composite-mux-clock}@y@[Wgpt5_fckti,composite-clock}VWgpt6_gate_fck@1000ti,composite-gate-clock}y[Xgpt6_mux_fck@1040ti,composite-mux-clock}@y@[Ygpt6_fckti,composite-clock}XYgpt7_gate_fck@1000ti,composite-gate-clock}y[Zgpt7_mux_fck@1040ti,composite-mux-clock}@y@[[gpt7_fckti,composite-clock}Z[gpt8_gate_fck@1000ti,composite-gate-clock} y[\gpt8_mux_fck@1040ti,composite-mux-clock}@y@[]gpt8_fckti,composite-clock}\]gpt9_gate_fck@1000ti,composite-gate-clock} y[^gpt9_mux_fck@1040ti,composite-mux-clock}@y@[_gpt9_fckti,composite-clock}^_per_32k_alwon_fckfixed-factor-clock}@ [`gpio6_dbck@1000ti,gate-clock}`y[gpio5_dbck@1000ti,gate-clock}`y[gpio4_dbck@1000ti,gate-clock}`y[gpio3_dbck@1000ti,gate-clock}`y[gpio2_dbck@1000ti,gate-clock}`y [wdt3_fck@1000ti,wait-gate-clock}`y [per_l4_ickfixed-factor-clock}? [agpio6_ick@1010ti,omap3-interface-clock}ay[gpio5_ick@1010ti,omap3-interface-clock}ay[gpio4_ick@1010ti,omap3-interface-clock}ay[gpio3_ick@1010ti,omap3-interface-clock}ay[gpio2_ick@1010ti,omap3-interface-clock}ay [wdt3_ick@1010ti,omap3-interface-clock}ay [uart3_ick@1010ti,omap3-interface-clock}ay [uart4_ick@1010ti,omap3-interface-clock}ay[gpt9_ick@1010ti,omap3-interface-clock}ay [gpt8_ick@1010ti,omap3-interface-clock}ay [gpt7_ick@1010ti,omap3-interface-clock}ay[gpt6_ick@1010ti,omap3-interface-clock}ay[gpt5_ick@1010ti,omap3-interface-clock}ay[gpt4_ick@1010ti,omap3-interface-clock}ay[gpt3_ick@1010ti,omap3-interface-clock}ay[gpt2_ick@1010ti,omap3-interface-clock}ay[mcbsp2_ick@1010ti,omap3-interface-clock}ay[mcbsp3_ick@1010ti,omap3-interface-clock}ay[mcbsp4_ick@1010ti,omap3-interface-clock}ay[mcbsp2_gate_fck@1000ti,composite-gate-clock}y[ mcbsp3_gate_fck@1000ti,composite-gate-clock}y[mcbsp4_gate_fck@1000ti,composite-gate-clock}y[emu_src_mux_ck@1140 ti,mux-clock}bcdy@[eemu_src_ckti,clkdm-gate-clock}e[fpclk_fck@1140ti,divider-clock}fy@pclkx2_fck@1140ti,divider-clock}fy@atclk_fck@1140ti,divider-clock}fy@traceclk_src_fck@1140 ti,mux-clock}bcdy@[gtraceclk_fck@1140ti,divider-clock}g y@secure_32k_fck fixed-clock[hgpt12_fckfixed-factor-clock}h wdt1_fckfixed-factor-clock}h security_l4_ick2fixed-factor-clock}? [iaes1_ick@a14ti,omap3-interface-clock}iy rng_ick@a14ti,omap3-interface-clock}iy sha11_ick@a14ti,omap3-interface-clock}iy des1_ick@a14ti,omap3-interface-clock}iy cam_mclk@f00ti,gate-clock}jyQcam_ick@f10!ti,omap3-no-wait-interface-clock}?y[csi2_96m_fck@f00ti,gate-clock}y[security_l3_ickfixed-factor-clock}> [kpka_ick@a14ti,omap3-interface-clock}ky icr_ick@a10ti,omap3-interface-clock}Jy des2_ick@a10ti,omap3-interface-clock}Jy mspro_ick@a10ti,omap3-interface-clock}Jy mailboxes_ick@a10ti,omap3-interface-clock}Jy ssi_l4_ickfixed-factor-clock}? [rsr1_fck@c00ti,wait-gate-clock}y [sr2_fck@c00ti,wait-gate-clock}y [sr_l4_ickfixed-factor-clock}? dpll2_fck@40ti,divider-clock}&y@[ldpll2_ck@4ti,omap3-dpll-clock}ly$@4z[mdpll2_m2_ck@44ti,divider-clock}myD[niva2_ck@0ti,wait-gate-clock}ny[modem_fck@a00ti,omap3-interface-clock}y [sad2d_ick@a10ti,omap3-interface-clock}>y [mad2d_ick@a18ti,omap3-interface-clock}>y [mspro_fck@a00ti,wait-gate-clock}y ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock}y [ossi_ssr_div_fck_3430es2@a40ti,composite-divider-clock}y @$[pssi_ssr_fck_3430es2ti,composite-clock}op[qssi_sst_fck_3430es2fixed-factor-clock}q [hsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clock}Iy [ssi_ick_3430es2@a10ti,omap3-ssi-interface-clock}ry [usim_gate_fck@c00ti,composite-gate-clock}E y [}sys_d2_ckfixed-factor-clock} [tomap_96m_d2_fckfixed-factor-clock}E [uomap_96m_d4_fckfixed-factor-clock}E [vomap_96m_d8_fckfixed-factor-clock}E [womap_96m_d10_fckfixed-factor-clock}E  [xdpll5_m2_d4_ckfixed-factor-clock}s [ydpll5_m2_d8_ckfixed-factor-clock}s [zdpll5_m2_d16_ckfixed-factor-clock}s [{dpll5_m2_d20_ckfixed-factor-clock}s [|usim_mux_fck@c40ti,composite-mux-clock(}tuvwxyz{|y @[~usim_fckti,composite-clock}}~usim_ick@c10ti,omap3-interface-clock}Ny  [dpll5_ck@d04ti,omap3-dpll-clock}y  $ L 4z[dpll5_m2_ck@d50ti,divider-clock}y P[ssgx_gate_fck@b00ti,composite-gate-clock}&y [core_d3_ckfixed-factor-clock}& [core_d4_ckfixed-factor-clock}& [core_d6_ckfixed-factor-clock}& [omap_192m_alwon_fckfixed-factor-clock}" [core_d2_ckfixed-factor-clock}& [sgx_mux_fck@b40ti,composite-mux-clock }*y @[sgx_fckti,composite-clock}[sgx_ick@b10ti,wait-gate-clock}>y [cpefuse_fck@a08ti,gate-clock}y [ts_fck@a08ti,gate-clock}@y [usbtll_fck@a08ti,wait-gate-clock}sy [usbtll_ick@a18ti,omap3-interface-clock}Jy [mmchs3_ick@a10ti,omap3-interface-clock}Jy [mmchs3_fck@a00ti,wait-gate-clock}y [dss1_alwon_fck_3430es2@e00ti,dss-gate-clock}yQ[dss_ick_3430es2@e10ti,omap3-dss-interface-clock}?y[usbhost_120m_fck@1400ti,gate-clock}sy[usbhost_48m_fck@1400ti,dss-gate-clock}0y[usbhost_ick@1410ti,omap3-dss-interface-clock}?y[clockdomainscore_l3_clkdmti,clockdomain}dpll3_clkdmti,clockdomain}dpll1_clkdmti,clockdomain}per_clkdmti,clockdomainh}emu_clkdmti,clockdomain}fdpll4_clkdmti,clockdomain}wkup_clkdmti,clockdomain$}dss_clkdmti,clockdomain}core_l4_clkdmti,clockdomain}cam_clkdmti,clockdomain}iva2_clkdmti,clockdomain}dpll2_clkdmti,clockdomain}md2d_clkdmti,clockdomain }dpll5_clkdmti,clockdomain}sgx_clkdmti,clockdomain}usbhost_clkdmti,clockdomain }counter@48320000ti,omap-counter32kyH2  counter_32kinterrupt-controller@48200000ti,omap3-intcyH [dma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmayH`  `dma[gpio@48310000ti,omap3-gpioyH1gpio1gpio@49050000ti,omap3-gpioyIgpio2gpio@49052000ti,omap3-gpioyI gpio3gpio@49054000ti,omap3-gpioyI@ gpio4gpio@49056000ti,omap3-gpioyI`!gpio5[ gpio@49058000ti,omap3-gpioyI"gpio6[serial@4806a000ti,omap3-uartyH H12txrxuart1lserial@4806c000ti,omap3-uartyHI34txrxuart2lserial@49020000ti,omap3-uartyIJ56txrxuart3ldefault)i2c@48070000 ti,omap3-i2cyH8txrx+i2c1'@twl@48yH  ti,twl4030default)audioti,twl4030-audiocodecrtcti,twl4030-rtc bciti,twl4030-bci 3A Mvacwatchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2 jvdd_ehciyw@w@^regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1y ' [regulator-vdacti,twl4030-vdacyw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1y:0[regulator-vmmc2ti,twl4030-vmmc2y:0regulator-vusb1v5ti,twl4030-vusb1v5[regulator-vusb1v8ti,twl4030-vusb1v8[regulator-vusb3v1ti,twl4030-vusb3v1[regulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2yw@w@^regulator-vsimti,twl4030-vsimyw@-[gpioti,twl4030-gpior~[twl4030-usbti,twl4030-usb [pwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypadmadcti,twl4030-madc[i2c@48072000 ti,omap3-i2cyH 9txrx+i2c2i2c@48060000 ti,omap3-i2cyH=txrx+i2c3default)mailbox@48094000ti,omap3-mailboxmailboxyH @ 2dsp D Ospi@48098000ti,omap2-mcspiyH A+mcspi1Z@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3default)spidev@0spidevhlyzspi@4809a000ti,omap2-mcspiyH B+mcspi2Z +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiyH [+mcspi3Z tx0rx0tx1rx1default)spidev@0spidevhlyzspi@480ba000ti,omap2-mcspiyH 0+mcspi4ZFGtx0rx01w@480b2000 ti,omap3-1wyH :hdq1wmmc@4809c000ti,omap3-hsmmcyH Smmc1=>txrxdefault) mmc@480b4000ti,omap3-hsmmcyH @Vmmc2/0txrxdefault)mmc@480ad000ti,omap3-hsmmcyH ^mmc3MNtxrx disabledmmu@480bd400ti,omap2-iommuyH mmu_isp[mmu@5d000000ti,omap2-iommuy]mmu_iva disabledwdt@48314000 ti,omap3-wdtyH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspyH@mpu ;< commontxrx!mcbsp1 txrx}fck disabledmcbsp@49022000ti,omap3-mcbspyI I mpusidetone>?commontxrxsidetone!mcbsp2mcbsp2_sidetone!"txrx}fckickokay[mcbsp@49024000ti,omap3-mcbspyI@I mpusidetoneYZcommontxrxsidetone!mcbsp3mcbsp3_sidetonetxrx}fckickokaydefault)mcbsp@49026000ti,omap3-mcbspyI`mpu 67 commontxrx!mcbsp4txrx}fck0 disabledmcbsp@48096000ti,omap3-mcbspyH `mpu QR commontxrx!mcbsp5txrx}fck disabledsham@480c3000ti,omap3-shamshamyH 0d1Erx disabledtimer@48318000ti,omap3430-timeryH1%timer1Atimer@49032000ti,omap3430-timeryI &timer2timer@49034000ti,omap3430-timeryI@'timer3timer@49036000ti,omap3430-timeryI`(timer4timer@49038000ti,omap3430-timeryI)timer5Ptimer@4903a000ti,omap3430-timeryI*timer6Ptimer@4903c000ti,omap3430-timeryI+timer7Ptimer@4903e000ti,omap3430-timeryI,timer8]Ptimer@49040000ti,omap3430-timeryI-timer9]timer@48086000ti,omap3430-timeryH`.timer10]timer@48088000ti,omap3430-timeryH/timer11]timer@48304000ti,omap3430-timeryH0@_timer12Ajusbhstll@48062000 ti,usbhs-tllyH N usb_tll_hsusbhshost@48064000ti,usbhs-hostyH@ usb_host_hs+ zehci-phyohci@48064400ti,ohci-omap3yHDLehci@48064800 ti,ehci-omapyHHMgpmc@6e000000ti,omap3430-gpmcgpmcynrxtx+0[nand@0,0ti,omap2-nand y sw$$#2E$Xf0uHH6+x-loader@0 X-Loaderybootloaders@80000U-Bootybootloaders_env@260000 U-Boot Envy&kernel@280000Kernely(@filesystem@680000 File Systemyhusb_otg_hs@480ab000ti,omap3-musbyH \]mcdma usb_otg_hs  usb2-phy2dss@48050000 ti,omap3-dssyHok dss_core}fck+default)dispc@48050400ti,omap3-dispcyH dss_dispc}fckencoder@4804fc00 ti,omap3-dsiyHH@H protophypll disabled dss_dsi1} fcksys_clkencoder@48050800ti,omap3-rfbiyH disabled dss_rfbi}fckickencoder@48050c00ti,omap3-vencyH  disabled dss_venc}fckportendpoint.[ ssi-controller@48058000 ti,omap3-ssissiokyHHsysgddGgdd_mpu+ }q ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portyHHtxrxCDssi-port@4805b000ti,omap3-ssi-portyHHtxrxEFpinmux@480025d8 ti,omap3-padconfpinctrl-singleyH%$+ *isp@480bc000 ti,omap3-ispyH H |9cl@ports+bandgap@48002524yH%$ti,omap34xx-bandgapL[target-module@480cb000ti,sysc-omap3430-srti,syscsmartreflex_coreyH $syscb}fck+ H smartreflex@0ti,omap3-smartreflex-coreytarget-module@480c9000ti,sysc-omap3430-srti,syscsmartreflex_mpu_ivayH $syscb}fck+ H smartreflex@480c9000ti,omap3-smartreflex-mpu-ivaytarget-module@50000000ti,sysc-omap2ti,syscyPrev}fckick+ P@thermal-zonescpu_thermaloN memory@80000000mmemoryyhsusb2_power_regregulator-fixed jhsusb2_vbusy2Z2Z p[hsusb2_phyusb-nop-xceiv [soundti,omap-twl4030 omap3beagleregulator-mmc2-sdio-poweronregulator-fixedjregulator-mmc2-sdio-powerony00  '[displaysamsung,lte430wq-f0cpanel-dpilcddefault)   portendpoint [panel-timingT@ %*/;H R_lvbacklightgpio-backlightdefault)    compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-pointscpu0-supplyinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinsphandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesstatusclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0bci3v1-supplyio-channelsio-channel-namesregulator-always-onti,use-ledsti,pullupsti,pulldownsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencyspi-cphati,dual-voltpbias-supplyvmmc-supplyvqmmc-supplycd-gpiosbus-widthnon-removablecap-power-off-card#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-size#sound-dai-cellsti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,wr-access-nslabelmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerremote-endpointdata-linesiommusti,phy-type#thermal-sensor-cellsti,sysc-maskpolling-delay-passivepolling-delaycoefficientsthermal-sensorsgpiostartup-delay-usreset-gpiosvcc-supplyti,modelti,mcbspenable-gpioshactivevactivehfront-porchhback-porchhsync-lenvback-porchvfront-porchvsync-lenhsync-activevsync-activede-activepixelclk-activedefault-on