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mcbsp1_fckti,composite-clock| Zmcbsp2_mux_fck@4ti,composite-mux-clock| xZ mcbsp2_fckti,composite-clock| Zmcbsp3_mux_fck@68ti,composite-mux-clock| xhZmcbsp3_fckti,composite-clock|Zmcbsp4_mux_fck@68ti,composite-mux-clock| xhZmcbsp4_fckti,composite-clock|Zclockdomainspinmux@a00 ti,omap3-padconfpinctrl-singlex \+ )pinmux_wlan_host_wkup_pinsFaes@480c5000 ti,omap3-aesaesxH PPABtxrxprm@48306000 ti,omap3-prmxH0`@ clocks+virt_16_8m_ck fixed-clockYZosc_sys_ck@d40 ti,mux-clock|x @Zsys_ck@1270ti,divider-clock|xpZsys_clkout1@d70ti,gate-clock|x pdpll3_x2_ckfixed-factor-clock|dpll3_m2x2_ckfixed-factor-clock|Zdpll4_x2_ckfixed-factor-clock|corex2_fckfixed-factor-clock|Zwkup_l4_ickfixed-factor-clock|ZNcorex2_d3_fckfixed-factor-clock|Zcorex2_d5_fckfixed-factor-clock|Zclockdomainscm@48004000 ti,omap3-cmxH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clockZ@virt_12m_ck fixed-clockZvirt_13m_ck fixed-clock]@Zvirt_19200000_ck fixed-clock$Zvirt_26000000_ck fixed-clockZvirt_38_4m_ck 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Zmcspi3_ick@a10ti,omap3-interface-clock|Jx Zmcspi2_ick@a10ti,omap3-interface-clock|Jx Zmcspi1_ick@a10ti,omap3-interface-clock|Jx Zi2c3_ick@a10ti,omap3-interface-clock|Jx Zi2c2_ick@a10ti,omap3-interface-clock|Jx Zi2c1_ick@a10ti,omap3-interface-clock|Jx Zuart2_ick@a10ti,omap3-interface-clock|Jx Zuart1_ick@a10ti,omap3-interface-clock|Jx  Zgpt11_ick@a10ti,omap3-interface-clock|Jx  Zgpt10_ick@a10ti,omap3-interface-clock|Jx  Zmcbsp5_ick@a10ti,omap3-interface-clock|Jx  Zmcbsp1_ick@a10ti,omap3-interface-clock|Jx  Zomapctrl_ick@a10ti,omap3-interface-clock|Jx Zdss_tv_fck@e00ti,gate-clock|8xZdss_96m_fck@e00ti,gate-clock|ExZdss2_alwon_fck@e00ti,gate-clock|xZdummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock|x ZKgpt1_mux_fck@c40ti,composite-mux-clock|@x @ZLgpt1_fckti,composite-clock|KLaes2_ick@a10ti,omap3-interface-clock|Jx Zwkup_32k_fckfixed-factor-clock|@ZMgpio1_dbck@c00ti,gate-clock|Mx Zsha12_ick@a10ti,omap3-interface-clock|Jx Zwdt2_fck@c00ti,wait-gate-clock|Mx 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sha11_ick@a14ti,omap3-interface-clock|ix des1_ick@a14ti,omap3-interface-clock|ix cam_mclk@f00ti,gate-clock|jxIcam_ick@f10!ti,omap3-no-wait-interface-clock|?xZcsi2_96m_fck@f00ti,gate-clock|xZsecurity_l3_ickfixed-factor-clock|>Zkpka_ick@a14ti,omap3-interface-clock|kx icr_ick@a10ti,omap3-interface-clock|Jx des2_ick@a10ti,omap3-interface-clock|Jx mspro_ick@a10ti,omap3-interface-clock|Jx mailboxes_ick@a10ti,omap3-interface-clock|Jx ssi_l4_ickfixed-factor-clock|?Zrsr1_fck@c00ti,wait-gate-clock|x Zsr2_fck@c00ti,wait-gate-clock|x Zsr_l4_ickfixed-factor-clock|?dpll2_fck@40ti,divider-clock|&x@Zldpll2_ck@4ti,omap3-dpll-clock|lx$@4rZmdpll2_m2_ck@44ti,divider-clock|mxDZniva2_ck@0ti,wait-gate-clock|nxZmodem_fck@a00ti,omap3-interface-clock|x Zsad2d_ick@a10ti,omap3-interface-clock|>x Zmad2d_ick@a18ti,omap3-interface-clock|>x Zmspro_fck@a00ti,wait-gate-clock|x ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock|x Zossi_ssr_div_fck_3430es2@a40ti,composite-divider-clock|x @$Zpssi_ssr_fck_3430es2ti,composite-clock|opZqssi_sst_fck_3430es2fixed-factor-clock|qZhsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clock|Ix Zssi_ick_3430es2@a10ti,omap3-ssi-interface-clock|rx Zusim_gate_fck@c00ti,composite-gate-clock|E x Z}sys_d2_ckfixed-factor-clock|Ztomap_96m_d2_fckfixed-factor-clock|EZuomap_96m_d4_fckfixed-factor-clock|EZvomap_96m_d8_fckfixed-factor-clock|EZwomap_96m_d10_fckfixed-factor-clock|E Zxdpll5_m2_d4_ckfixed-factor-clock|sZydpll5_m2_d8_ckfixed-factor-clock|sZzdpll5_m2_d16_ckfixed-factor-clock|sZ{dpll5_m2_d20_ckfixed-factor-clock|sZ|usim_mux_fck@c40ti,composite-mux-clock(|tuvwxyz{|x @Z~usim_fckti,composite-clock|}~usim_ick@c10ti,omap3-interface-clock|Nx  Zdpll5_ck@d04ti,omap3-dpll-clock|x  $ L 4rZdpll5_m2_ck@d50ti,divider-clock|x PZssgx_gate_fck@b00ti,composite-gate-clock|&x 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ti,omap3-1wxH :hdq1wmmc@4809c000ti,omap3-hsmmcxH Smmc14=>txrxANZgdefault!mmc@480b4000ti,omap3-hsmmcxH @Vmmc2/0txrxmmc@480ad000ti,omap3-hsmmcxH ^mmc3MNtxrxNqgdefault!+wlcore@2 ti,wl1271x mmu@480bd400ti,omap2-iommuxH mmu_ispZmmu@5d000000ti,omap2-iommux]mmu_iva disabledwdt@48314000 ti,omap3-wdtxH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspxH@mpu ;< commontxrxmcbsp1 txrx|fck disabledmcbsp@49022000ti,omap3-mcbspxI I mpusidetone>?commontxrxsidetonemcbsp2mcbsp2_sidetone!"txrx|fckick disabledmcbsp@49024000ti,omap3-mcbspxI@I mpusidetoneYZcommontxrxsidetonemcbsp3mcbsp3_sidetonetxrx|fckick disabledmcbsp@49026000ti,omap3-mcbspxI`mpu 67 commontxrxmcbsp4txrx|fck disabledmcbsp@48096000ti,omap3-mcbspxH `mpu QR commontxrxmcbsp5txrx|fck disabledsham@480c3000ti,omap3-shamshamxH 0d1Erxtimer@48318000ti,omap3430-timerxH1%timer1timer@49032000ti,omap3430-timerxI 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fcksys_clkencoder@48050800ti,omap3-rfbixH disabled dss_rfbi|fckickencoder@48050c00ti,omap3-vencxH  disabled dss_venc|fcktv_dac_clkssi-controller@48058000 ti,omap3-ssissiokxHHsysgddGgdd_mpu+ |q ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portxHHtxrxCDssi-port@4805b000ti,omap3-ssi-portxHHtxrxEFserial@49042000ti,omap3-uartxI PQRtxrxuart4l disabledregulator-abb-mpu ti,abb-v1 iabb_mpu_iva+xH0rH0hbase-addressint-address|`&sO7pinmux@480025a0 ti,omap3-padconfpinctrl-singlexH%\+ )pinmux_mmc3_2_pins(F8DFHBZisp@480bc000 ti,omap3-ispxH H 2b9ports+bandgap@48002524xH%$ti,omap36xx-bandgapEZtarget-module@480cb000ti,sysc-omap3630-srti,syscsmartreflex_corexH 8sysc[ h|fck+ H smartreflex@0ti,omap3-smartreflex-corextarget-module@480c9000ti,sysc-omap3630-srti,syscsmartreflex_mpu_ivaxH 8sysc[ h|fck+ H smartreflex@480c9000ti,omap3-smartreflex-mpu-ivaxtarget-module@50000000ti,sysc-omap4ti,syscxPP revsysc v h|fckick+ Pthermal-zonescpu_thermalN regulator-vddvarioregulator-fixed ivddvarioZregulator-vdd33aregulator-fixedivdd33aZmemory@80000000lmemoryx wl12xx_vmmcdefault!regulator-fixedivwl1271xw@w@ pZ compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2serial3device_typeregclocksclock-namesclock-latencyoperating-pointscpu0-supplyinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinsphandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0bci3v1-supplyio-channelsio-channel-namesti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplyvqmmc-supplybus-widthnon-removablecap-power-off-cardref-clock-frequency#iommu-cellsti,#tlb-entriesstatusreg-namesinterrupt-namesti,buffer-size#sound-dai-cellsti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureremote-wakeup-connectedgpmc,num-csgpmc,num-waitpinsbank-widthgpmc,device-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsgpmc,wr-data-mux-bus-nsgpmc,wr-access-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressreg-shiftcurrent-speedgpmc,mux-add-datagpmc,wait-pinmultipointnum-epsram-bitsinterface-typeusb-phypowerti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-type#thermal-sensor-cellsti,sysc-maskti,sysc-sidleti,sysc-midlepolling-delay-passivepolling-delaycoefficientsthermal-sensorsregulator-always-ongpiostartup-delay-usenable-active-high