8( (google,veyron-fievel-rev8google,veyron-fievel-rev7google,veyron-fievel-rev6google,veyron-fievel-rev5google,veyron-fievel-rev4google,veyron-fievel-rev3google,veyron-fievel-rev2google,veyron-fievel-rev1google,veyron-fievel-rev0google,veyron-fievelgoogle,veyronrockchip,rk3288&7Google Fievelaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/dwmmc@ff0f0000k/dwmmc@ff0c0000q/dwmmc@ff0d0000w/dwmmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12'@5<rV bcpu@501cpuarm,cortex-a12'@5<rbcpu@502cpuarm,cortex-a12'@5<rbcpu@503cpuarm,cortex-a12'@5<rbcpu-opp-tableoperating-points-v2jbopp-126000000u| opp-216000000u | opp-408000000uQ| opp-600000000u#F| opp-696000000u)||~opp-816000000u0,|B@opp-1008000000u<|opp-1200000000uG|opp-1416000000uTfr|Oopp-1512000000uZJ|opp-1608000000u_"| opp-1704000000ue|popp-1800000000ukI|\amba simple-busdma-controller@ff250000arm,pl330arm,primecell%@5 apb_pclkbdma-controller@ff600000arm,pl330arm,primecell`@5 apb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@5 apb_pclkbcreserved-memorydma-unusable@fe000000oscillator fixed-clockn6xin24mb timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H 5 a timerpclkdisplay-subsystemrockchip,display-subsystem5 dwmmc@ff0c0000rockchip,rk3288-dw-mshc;р 5Drvbiuciuciu-driveciu-sampleI  @Treset disableddwmmc@ff0d0000rockchip,rk3288-dw-mshc;р 5Eswbiuciuciu-driveciu-sampleI ! @Tresetokay`j{ default btmrvl@2marvell,sd8897-bt& defaultdwmmc@ff0e0000rockchip,rk3288-dw-mshc;р 5Ftxbiuciuciu-driveciu-sampleI "@Treset disableddwmmc@ff0f0000rockchip,rk3288-dw-mshc;р 5Guybiuciuciu-driveciu-sampleI #@Tresetokay`0B`kdefault saradc@ff100000rockchip,saradc $z5I[saradcapb_pclkW Tsaradc-apb disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi5ARspiclkapb_pclk  txrx ,default disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi5BSspiclkapb_pclk txrx -default ! disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi5CTspiclkapb_pclktxrx .default"#$%okay flash@0jedec,spi-nori2c@ff140000rockchip,rk3288-i2c >i2c5Mdefault&okay2dtpm@20infineon,slb9645tt i2c@ff150000rockchip,rk3288-i2c ?i2c5Odefault' disabledi2c@ff160000rockchip,rk3288-i2c @i2c5Pdefault(okay2,ts3a227e@3b ti,ts3a227e;&)default*bi2c@ff170000rockchip,rk3288-i2c Ai2c5Qdefault+ disabledserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 75MUbaudclkapb_pclkdefault ,-.okayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 85NVbaudclkapb_pclkdefault/okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 95OWbaudclkapb_pclkdefault0okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :5PXbaudclkapb_pclkdefault1 disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;5QYbaudclkapb_pclkdefault2 disabledthermal-zonesreserve_thermal)?M3cpu_thermal)d?M3tripscpu_alert0]pipassiveb4cpu_alert1]$ipassiveb5cpu_crit]i criticalcooling-mapsmap0t40ymap1t50ygpu_thermal)d?M3tripsgpu_alert0]4ipassiveb6gpu_crit]i criticalcooling-mapsmap0t6 y7tsadc@ff280000rockchip,rk3288-tsadc( %5HZtsadcapb_pclk Ttsadc-apbinitdefaultsleep898:Hokayb3ethernet@ff290000rockchip,rk3288-gmac)macirqeth_wake_irq:85fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB Tstmmacethokay(;?inputL<Wrgmii`=default>?@Akt0 } 'u0mdio0snps,dwmac-mdioethernet-phy@1b<usb@ff500000 generic-ehciP 5usbhostBusbokayusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 5otghostC usb2-phyokay usb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 5otghost!3B@@ D usb2-phyokayz(D usb@ff5c0000 generic-ehci\ 5usbhost disabledi2c@ff650000rockchip,rk3288-i2ce <i2c5LdefaultEokay2dpmic@1brockchip,rk808xin32kwifibt_32kin&)default FGHQr~IJ JKbregulatorsDCDC_REG1vdd_arm'9 qQ iqb regulator-state-mem~DCDC_REG2vdd_gpu'9 5Qiqbregulator-state-mem~DCDC_REG3 vcc135_ddr'regulator-state-memDCDC_REG4vcc_18'9w@Qw@bregulator-state-memw@LDO_REG3vdd_10'9B@QB@regulator-state-memB@LDO_REG7 vdd10_lcd'9B@QB@regulator-state-mem~SWITCH_REG1 vcc33_lcd'baregulator-state-mem~LDO_REG6 vcc18_codec'9w@Qw@bbregulator-state-mem~LDO_REG2'9w@Qw@ vdd18_lcdtregulator-state-mem~LDO_REG8'92ZQ2Z vcc33_ccdregulator-state-mem~SWITCH_REG2 vcc33_lanb=i2c@ff660000rockchip,rk3288-i2cf =i2c5NdefaultLokay2 max98090@10maxim,max98090&Mmclk5qdefaultNbpwm@ff680000rockchip,rk3288-pwmhdefaultO5_pwm disabledpwm@ff680010rockchip,rk3288-pwmhdefaultP5_pwmokaybpwm@ff680020rockchip,rk3288-pwmh defaultQ5_pwm disabledpwm@ff680030rockchip,rk3288-pwmh0defaultR5_pwm disabledbus_intmem@ff700000 mmio-sramppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsbpower-controller!rockchip,rk3288-power-controllerh( bfpd_vio@9 5chgfdehilkj$STUVWXYZ[pd_hevc@11 5op\]pd_video@12 5^pd_gpu@13 5_`reboot-modesyscon-reboot-modeRBRBRB "RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv:.Hjk$;#gׄeрxhрxhbsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwb:edp-phyrockchip,rk3288-dp-phy5h24mP disabledbvio-domains"rockchip,rk3288-io-voltage-domainokay[Iep~IIabusbphyrockchip,rk3288-usb-phyokayusb-phy@320P 5]phyclk Tphy-resetbDusb-phy@334P45^phyclk Tphy-resetbBusb-phy@348PH5_phyclk Tphy-resetbCwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt5p Ookaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif hclkmclk5Tctx 6defaultd: disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s 5cctxrxi2s_hclki2s_clk5Rdefaulteokaybcypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 5}aclkhclksclkapb_pclk Tcrypto-rstokayiommu@ff900800rockchip,iommu@ iep_mmu5 aclkiface  disablediommu@ff914000rockchip,iommu @P isp_mmu5 aclkiface   disabledrga@ff920000rockchip,rk3288-rga 5jaclkhclksclk /f ilm Tcoreaxiahbvop@ff930000rockchip,rk3288-vop 5aclk_vopdclk_vophclk_vop /f def Taxiahbdclk =gokayportb endpoint@0 Dhb{endpoint@1 Dibwendpoint@2 Djbqendpoint@3 Dkbtiommu@ff930300rockchip,iommu  vopb_mmu5 aclkiface /f  okaybgvop@ff940000rockchip,rk3288-vop 5aclk_vopdclk_vophclk_vop /f  Taxiahbdclk =l disabledportb endpoint@0 Dmb|endpoint@1 Dnbxendpoint@2 Dobrendpoint@3 Dpbuiommu@ff940300rockchip,iommu  vopl_mmu5 aclkiface /f   disabledblmipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ 5~d refpclk /f : disabledportsportendpoint@0 Dqbjendpoint@1 Drbolvds@ff96c000rockchip,rk3288-lvds@5g pclk_lvdslcdcs /f : disabledportsport@0endpoint@0 Dtbkendpoint@1 Dubpdp@ff970000rockchip,rk3288-dp@ b5icdppclkvdpoTdp: disabledportsport@0endpoint@0 Dwbiendpoint@1 Dxbnhdmi@ff980000rockchip,rk3288-dw-hdmi: g5hmniahbisfrcec /f okaydefaultunwedgeyzportsportendpoint@0 D{bhendpoint@1 D|bmvideo-codec@ff9a0000rockchip,rk3288-vpu   vepuvdpu5 aclkhclk =} /f iommu@ff9a0800rockchip,iommu vpu_mmu5 aclkiface  /f b}iommu@ff9c0440rockchip,iommu @@@ o hevc_mmu5 aclkiface  disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ jobmmugpu5~ /f okay Tb7gpu-opp-tableoperating-points-v2b~opp-100000000u|~opp-200000000u |~opp-300000000u|B@opp-400000000uׄ|opp-600000000u#F|qos@ffaa0000syscon b_qos@ffaa0080syscon b`qos@ffad0000syscon bTqos@ffad0100syscon bUqos@ffad0180syscon bVqos@ffad0400syscon bWqos@ffad0480syscon bXqos@ffad0500syscon bSqos@ffad0800syscon bYqos@ffad0880syscon bZqos@ffad0900syscon b[qos@ffae0000syscon b^qos@ffaf0000syscon b\qos@ffaf0080syscon b]efuse@ffb40000rockchip,rk3288-efuse 5q pclk_efusecpu_leakage@17interrupt-controller@ffc01000 arm,gic-400 ` u@ @ `   bpinctrlrockchip,rk3288-pinctrl:defaultsleepgpio0@ff750000rockchip,gpio-banku Q5@   ` u PMIC_SLEEP_APDDRIO_PWROFFDDRIO_RETENTS3A227E_INT_LPMIC_INT_LPWR_KEY_LHUB_USB1_nFALUTPHY_PMEBPHY_INTREC_MODE_LOTP_OUTUSB_OTG_POWER_ENAP_WARM_RESET_HUSB_OTG_nFALUTI2C0_SDA_PMICI2C0_SCL_PMICDEVMODE_LUSB_INTb)gpio1@ff780000rockchip,gpio-bankx R5A   ` ugpio2@ff790000rockchip,gpio-banky S5B   ` ui CONFIG0CONFIG1CONFIG2CONFIG3EMMC_RST_LBL_PWR_ENTOUCH_INTTOUCH_RSTI2C3_SCL_TPI2C3_SDA_TPbgpio3@ff7a0000rockchip,gpio-bankz T5C   ` u FLASH0_D0FLASH0_D1FLASH0_D2FLASH0_D3FLASH0_D4FLASH0_D5FLASH0_D6FLASH0_D7VCC5V_GOOD_HFLASH0_CS2/EMMC_CMDFLASH0_DQS/EMMC_CLKOPHY_TXD2PHY_TXD3MAC_RXD2MAC_RXD3PHY_TXD0PHY_TXD1MAC_RXD0MAC_RXD1gpio4@ff7b0000rockchip,gpio-bank{ U5D   ` u MAC_MDCMAC_RXDVMAC_RXERMAC_CLKPHY_TXENMAC_MDIOMAC_RXCLKPHY_RSTPHY_TXCLKUART0_RXDUART0_TXDUART0_CTS_LUART0_RTS_LSDIO0_D0SDIO0_D1SDIO0_D2SDIO0_D3SDIO0_CMDSDIO0_CLKBT_DEV_WAKEWIFI_ENABLE_HBT_ENABLE_LWIFI_HOST_WAKEBT_HOST_WAKEbgpio5@ff7c0000rockchip,gpio-bank| V5E   ` u USB_OTG_CTL1HUB_USB2_CTL1HUB_USB2_PWR_ENHUB_USB_ILIM_SELUSB_OTG_STATUS_LHUB_USB1_CTL1HUB_USB1_PWR_ENVCC50_HDMI_ENbgpio6@ff7d0000rockchip,gpio-bank} W5F   ` u I2S0_SCLKI2S0_LRCK_RXI2S0_LRCK_TXI2S0_SDII2S0_SDO0HP_DET_HINT_CODECI2S0_CLKI2C2_SDAI2C2_SCLMICDETHUB_USB2_nFALUTUSB_OTG_ILIM_SELbMgpio7@ff7e0000rockchip,gpio-bank~ X5G   ` u LCD_BL_PWMPWM_LOGBL_ENPWR_LED1TPM_INT_HSPK_ONFW_WP_APCPU_NMIDVSOKEDP_HPDDVS1LCD_ENDVS2HDMI_CECI2C4_SDAI2C4_SCLI2C5_SDA_HDMII2C5_SCL_HDMI5V_DRVUART2_RXDUART2_TXDbJgpio8@ff7f0000rockchip,gpio-bank Y5H   ` u^ RAM_ID0RAM_ID1RAM_ID2RAM_ID3I2C1_SDA_TPMI2C1_SCL_TPMSPI2_CLKSPI2_CS0SPI2_RXDSPI2_TXDhdmihdmi-cec-c0 hdmi-cec-c7 hdmi-ddc byhdmi-ddc-unwedge bzvcc50-hdmi-en bpcfg-output-low bpcfg-pull-up bpcfg-pull-down bpcfg-pull-none bpcfg-pull-none-12ma  bsleepglobal-pwroff bddrio-pwroff bddr0-retention bddr1-retention edpedp-hpd  i2c0i2c0-xfer bEi2c1i2c1-xfer b&i2c2i2c2-xfer   bLi2c3i2c3-xfer b'i2c4i2c4-xfer b(i2c5i2c5-xfer b+i2s0i2s0-bus` belcdclcdc-ctl@ bssdmmcsdmmc-clk sdmmc-cmd sdmmc-cd sdmmc-bus1 sdmmc-bus4@ sdio0sdio0-bus1 sdio0-bus4@ bsdio0-cmd bsdio0-clk bsdio0-cd sdio0-wp sdio0-pwr sdio0-bkpwr sdio0-int wifienable-h bbt-enable-l bbt-host-wake bt-host-wake-l bbt-dev-wake-sleep bbt-dev-wake-awake bsdio1sdio1-bus1 sdio1-bus4@ sdio1-cd sdio1-wp sdio1-bkpwr sdio1-int sdio1-cmd sdio1-clk sdio1-pwr  emmcemmc-clk bemmc-cmd bemmc-pwr  emmc-bus1 emmc-bus4@ emmc-bus8 bemmc-reset  bspi0spi0-clk  bspi0-cs0  bspi0-tx bspi0-rx bspi0-cs1 spi1spi1-clk  bspi1-cs0  b!spi1-rx b spi1-tx bspi2spi2-cs1 spi2-clk b"spi2-cs0 b%spi2-rx b$spi2-tx  b#uart0uart0-xfer b,uart0-cts b-uart0-rts b.uart1uart1-xfer  b/uart1-cts  uart1-rts  uart2uart2-xfer b0uart3uart3-xfer b1uart3-cts  uart3-rts  uart4uart4-xfer b2uart4-cts  uart4-rts  tsadcotp-gpio b8otp-out b9pwm0pwm0-pin bOpwm1pwm1-pin bPpwm2pwm2-pin bQpwm3pwm3-pin bRgmacrgmii-pins  b>rmii-pins phy-rst b?phy-pmeb b@phy-int bAspdifspdif-tx  bdpcfg-pull-none-drv-8ma  bpcfg-pull-up-drv-8ma  pcfg-output-high bbuttonspwr-key-l bpmicpmic-int-l bFdvs-1  bGdvs-2 bHrebootap-warm-reset-h brecovery-switchrec-mode-l tpmtpm-int-h write-protectfw-wp-ap codechp-det bint-codec bNmic-det  bheadsetts3a227e-int-l b*buck-5vdrv-5v bledspwr-led1-on bpwr-led1-blink busb-bc12usb-otg-ilim-sel busb-usb-ilim-sel busb-hosthub_usb1_pwr_en bhub_usb2_pwr_en busb_otg_pwr_en bchosen serial2:115200n8memorymemorypower-button gpio-keysdefaultpower Power ) !t ,dgpio-restart gpio-restart ) default >emmc-pwrseqmmc-pwrseq-emmcdefault G bsdio-pwrseqmmc-pwrseq-simple5 ext_clockdefault Gb vcc-5vregulator-fixedvcc_5v'9LK@QLK@ S JdefaultbKvcc33-sysregulator-fixed vcc33_sys'92ZQ2Zbvcc50-hdmiregulator-fixed vcc50_hdmi' fK S defaultvdd-logicpwm-regulator vdd_logic q v { '9~Qpisound!rockchip,rockchip-audio-max98090default VEYRON-I2S   M M  vccsysregulator-fixedvccsys'vcc33-ioregulator-fixed' vcc33_iobIvcc5-host1-regulatorregulator-fixed S default vcc5_host1'vcc5-host2-regulatorregulator-fixed S default vcc5_host2'vcc5v-otg-regulatorregulator-fixed S ) default vcc5_otg'external-gmac-clock fixed-clocksY@ ext_gmacb; #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendportsmax-frequencyfifo-depthreset-namesbus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablepinctrl-namespinctrl-0sd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplymarvell,wakeup-pincap-mmc-highspeedrockchip,default-sample-phasedisable-wpmmc-hs200-1_8v#io-channel-cellsdmasdma-namesrx-sample-delay-nsspi-max-frequencyi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedti,micbiasreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesassigned-clocksassigned-clock-parentsclock_in_outphy-handlephy-modephy-supplyrx_delaytx_delaysnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-uswakeup-sourcephysphy-namesneeds-reset-on-resumedr_modesnps,reset-phy-on-wakesnps,need-phy-for-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc12-supplyvddio-supplyvcc10-supplydvs-gpiosvcc11-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supplyaudio-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsgpio-line-namesrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathlabellinux,codedebounce-intervalpriorityreset-gpiosenable-active-highvin-supplypwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unitrockchip,modelrockchip,i2s-controllerrockchip,audio-codecrockchip,hp-det-gpiosrockchip,mic-det-gpiosrockchip,headset-codec