8( Kgoogle,veyron-pinky-rev2google,veyron-pinkygoogle,veyronrockchip,rk3288& 7Google Pinkyaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/dwmmc@ff0f0000k/dwmmc@ff0c0000q/dwmmc@ff0d0000w/dwmmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000/spi@ff110000/ec@0/i2c-tunnelarm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12 -@;Br\ hcpu@501cpuarm,cortex-a12 -@;Brhcpu@502cpuarm,cortex-a12 -@;Brhcpu@503cpuarm,cortex-a12 -@;Brhcpu-opp-tableoperating-points-v2phopp-126000000{ opp-216000000{  opp-408000000{Q opp-600000000{#F opp-696000000{)|~opp-816000000{0,B@opp-1008000000{<opp-1200000000{Gopp-1416000000{TfrOopp-1512000000{ZJopp-1608000000{_" opp-1704000000{epopp-1800000000{kI\amba simple-busdma-controller@ff250000arm,pl330arm,primecell%@; apb_pclkh dma-controller@ff600000arm,pl330arm,primecell`@; apb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@; apb_pclkhbreserved-memorydma-unusable@fe000000oscillator fixed-clockn6xin24mh timerarm,armv7-timer0   n6$timer@ff810000rockchip,rk3288-timer  H ; a timerpclkdisplay-subsystemrockchip,display-subsystem; dwmmc@ff0c0000rockchip,rk3288-dw-mshcAр ;Drvbiuciuciu-driveciu-sampleO  @Zresetokayfp  Z default( 2 dwmmc@ff0d0000rockchip,rk3288-dw-mshcAр ;Eswbiuciuciu-driveciu-sampleO ! @Zresetokayf;H^idefault ( dwmmc@ff0e0000rockchip,rk3288-dw-mshcAр ;Ftxbiuciuciu-driveciu-sampleO "@Zreset disableddwmmc@ff0f0000rockchip,rk3288-dw-mshcAр ;Guybiuciuciu-driveciu-sampleO #@Zresetokayfpwidefault(saradc@ff100000rockchip,saradc $;I[saradcapb_pclkW Zsaradc-apb disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi;ARspiclkapb_pclk txrx ,default(!"#$okayec@0google,cros-ec-spi& default(%-i2c-tunnelgoogle,cros-ec-i2c-tunnelsbs-battery@bsbs,sbs-battery keyboard-controllergoogle,cros-ec-keyb, ?@Y};0DY1 d>"A#( C  \=@V B |)<?   + ^a !%$' & + ,./-32*5 4 9    8 l j6  g ispi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi;BSspiclkapb_pclk txrx -default(&'() disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi;CTspiclkapb_pclk  txrx .default(*+,-okayf flash@0jedec,spi-nori2c@ff140000rockchip,rk3288-i2c >i2c;Mdefault(.okayy2dtpm@20infineon,slb9645tt i2c@ff150000rockchip,rk3288-i2c ?i2c;Odefault(/okayy2,i2c@ff160000rockchip,rk3288-i2c @i2c;Pdefault(0okayy2,ts3a227e@3b ti,ts3a227e;&1default(2htrackpad@15elan,ekth3000& default(34i2c@ff170000rockchip,rk3288-i2c Ai2c;Qdefault(5 disabledserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 7;MUbaudclkapb_pclkdefault (678okayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 8;NVbaudclkapb_pclkdefault(9okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 9;OWbaudclkapb_pclkdefault(:okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :;PXbaudclkapb_pclkdefault(; disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;;QYbaudclkapb_pclkdefault(< disabledthermal-zonesreserve_thermal=cpu_thermald=tripscpu_alert0/p;passiveh>cpu_alert1/$;passiveh?cpu_crit/; criticalcooling-mapsmap0F>0Kmap1F?0Kgpu_thermald=tripsgpu_alert0/4;passiveh@gpu_crit/; criticalcooling-mapsmap0F@ KAtsadc@ff280000rockchip,rk3288-tsadc( %;HZtsadcapb_pclk Ztsadc-apbinitdefaultsleep(BZCdBnDH disabledh=ethernet@ff290000rockchip,rk3288-gmac)macirqeth_wake_irqD8;fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB Zstmmaceth disabledusb@ff500000 generic-ehciP ;usbhostEusbokayusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T ;otghostF usb2-phyokay.usb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X ;otghostEWf@@ G usb2-phyokayuzG.usb@ff5c0000 generic-ehci\ ;usbhost disabledi2c@ff650000rockchip,rk3288-i2ce <i2c;Ldefault(Hokayy2dpmic@1brockchip,rk808xin32kwifibt_32kin&1default(IJ4+8JDJhregulatorsDCDC_REG1Qvdd_arm`t q qh regulator-state-memDCDC_REG2Qvdd_gpu`t 5qhregulator-state-memDCDC_REG3 Qvcc135_ddr`tregulator-state-memDCDC_REG4Qvcc_18`tw@w@hregulator-state-memw@LDO_REG1 Qvcc33_io`t2Z2Zh4regulator-state-mem2ZLDO_REG3Qvdd_10`tB@B@regulator-state-memB@LDO_REG7Qvdd10_lcd_pwren_h`t&%&%regulator-state-memSWITCH_REG1 Qvcc33_lcd`th`regulator-state-memLDO_REG6 Qvcc18_codec`tw@w@haregulator-state-memLDO_REG4 Qvccio_sdw@2Zhregulator-state-memLDO_REG5 Qvcc33_sd2Z2Zhregulator-state-memLDO_REG8 Qvcc33_ccd`t2Z2Zregulator-state-memSWITCH_REG2`t Qvcc18_lcdregulator-state-memi2c@ff660000rockchip,rk3288-i2cf =i2c;Ndefault(Kokayy2 max98090@10maxim,max98090&Lmclk;qdefault(Mhpwm@ff680000rockchip,rk3288-pwmhdefault(N;_pwmokayhpwm@ff680010rockchip,rk3288-pwmhdefault(O;_pwmokayhpwm@ff680020rockchip,rk3288-pwmh default(P;_pwm disabledpwm@ff680030rockchip,rk3288-pwmh0default(Q;_pwm disabledbus_intmem@ff700000 mmio-sramppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdshpower-controller!rockchip,rk3288-power-controller#uh hepd_vio@9 ;chgfdehilkj$7RSTUVWXYZpd_hevc@11 ;op7[\pd_video@12 ;7]pd_gpu@13 ;7^_reboot-modesyscon-reboot-mode>ERBQRB_RB oRBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruvD{Hujk$#gׄeрxhрxhhsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwhDedp-phyrockchip,rk3288-dp-phy;h24mokayhuio-domains"rockchip,rk3288-io-voltage-domainokay444` a usbphyrockchip,rk3288-usb-phyokayusb-phy@320 ;]phyclk Zphy-resethGusb-phy@3344;^phyclk Zphy-resethEusb-phy@348H;_phyclk Zphy-resethFwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt;p Ookaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif  hclkmclk;Tbtx 6default(cD disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s  5bbtxrxi2s_hclki2s_clk;Rdefault(d - Hokayhcypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 ;}aclkhclksclkapb_pclk Zcrypto-rstokayiommu@ff900800rockchip,iommu@ iep_mmu; aclkiface b disablediommu@ff914000rockchip,iommu @P isp_mmu; aclkiface b o disabledrga@ff920000rockchip,rk3288-rga ;jaclkhclksclk e ilm Zcoreaxiahbvop@ff930000rockchip,rk3288-vop ;aclk_vopdclk_vophclk_vop e def Zaxiahbdclk fokayporth endpoint@0 gh{endpoint@1 hhvendpoint@2 ihpendpoint@3 jhsiommu@ff930300rockchip,iommu  vopb_mmu; aclkiface e  bokayhfvop@ff940000rockchip,rk3288-vop ;aclk_vopdclk_vophclk_vop e  Zaxiahbdclk kokayporth endpoint@0 lh|endpoint@1 mhwendpoint@2 nhqendpoint@3 ohtiommu@ff940300rockchip,iommu  vopl_mmu; aclkiface e  bokayhkmipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ ;~d refpclk e D disabledportsportendpoint@0 phiendpoint@1 qhnlvds@ff96c000rockchip,rk3288-lvds@;g pclk_lvdslcdc(r e D disabledportsport@0endpoint@0 shjendpoint@1 thodp@ff970000rockchip,rk3288-dp@ b;icdppclkudpoZdpDokay portsport@0endpoint@0 vhhendpoint@1 whmport@1endpoint@0 xhhdmi@ff980000rockchip,rk3288-dw-hdmi D g;hmniahbisfrcec e okaydefaultunwedge(yZzportsportendpoint@0 {hgendpoint@1 |hlvideo-codec@ff9a0000rockchip,rk3288-vpu   vepuvdpu; aclkhclk } e iommu@ff9a0800rockchip,iommu vpu_mmu; aclkiface b e h}iommu@ff9c0440rockchip,iommu @@@ o hevc_mmu; aclkiface b disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ jobmmugpu; ~ e okay hAgpu-opp-tableoperating-points-v2h~opp-100000000{~opp-200000000{ ~opp-300000000{B@opp-400000000{ׄopp-600000000{#Fqos@ffaa0000syscon h^qos@ffaa0080syscon h_qos@ffad0000syscon hSqos@ffad0100syscon hTqos@ffad0180syscon hUqos@ffad0400syscon hVqos@ffad0480syscon hWqos@ffad0500syscon hRqos@ffad0800syscon hXqos@ffad0880syscon hYqos@ffad0900syscon hZqos@ffae0000syscon h]qos@ffaf0000syscon h[qos@ffaf0080syscon h\efuse@ffb40000rockchip,rk3288-efuse ;q pclk_efusecpu_leakage@17interrupt-controller@ffc01000 arm,gic-400  @ @ `   hpinctrlrockchip,rk3288-pinctrlDdefaultsleep(Zgpio0@ff750000rockchip,gpio-banku Q;@    h1gpio1@ff780000rockchip,gpio-bankx R;A    gpio2@ff790000rockchip,gpio-banky S;B    gpio3@ff7a0000rockchip,gpio-bankz T;C    gpio4@ff7b0000rockchip,gpio-bank{ U;D    hgpio5@ff7c0000rockchip,gpio-bank| V;E    gpio6@ff7d0000rockchip,gpio-bank} W;F    hLgpio7@ff7e0000rockchip,gpio-bank~ X;G    h gpio8@ff7f0000rockchip,gpio-bank Y;H    hdmihdmi-cec-c0 hdmi-cec-c7 hdmi-ddc hyhdmi-ddc-unwedge hzpcfg-output-low hpcfg-pull-up hpcfg-pull-down -hpcfg-pull-none <hpcfg-pull-none-12ma < I hsleepglobal-pwroff hddrio-pwroff hddr0-retention hddr1-retention edpedp-hpd  i2c0i2c0-xfer hHi2c1i2c1-xfer h.i2c2i2c2-xfer   hKi2c3i2c3-xfer h/i2c4i2c4-xfer h0i2c5i2c5-xfer h5i2s0i2s0-bus` hdlcdclcdc-ctl@ hrsdmmcsdmmc-clk hsdmmc-cmd hsdmmc-cd sdmmc-bus1 sdmmc-bus4@ hsdmmc-cd-disabled hsdmmc-cd-gpio hsdmmc-wp-gpio  hsdio0sdio0-bus1 sdio0-bus4@ hsdio0-cmd hsdio0-clk hsdio0-cd sdio0-wp sdio0-pwr sdio0-bkpwr sdio0-int wifienable-h hbt-enable-l hbt-host-wake hbt-host-wake-l bt-dev-wake-sleep hbt-dev-wake-awake hsdio1sdio1-bus1 sdio1-bus4@ sdio1-cd sdio1-wp sdio1-bkpwr sdio1-int sdio1-cmd sdio1-clk sdio1-pwr  emmcemmc-clk hemmc-cmd hemmc-pwr  emmc-bus1 emmc-bus4@ emmc-bus8 hemmc-reset  hspi0spi0-clk  h!spi0-cs0  h$spi0-tx h"spi0-rx h#spi0-cs1 spi1spi1-clk  h&spi1-cs0  h)spi1-rx h(spi1-tx h'spi2spi2-cs1 spi2-clk h*spi2-cs0 h-spi2-rx h,spi2-tx  h+uart0uart0-xfer h6uart0-cts h7uart0-rts h8uart1uart1-xfer  h9uart1-cts  uart1-rts  uart2uart2-xfer h:uart3uart3-xfer h;uart3-cts  uart3-rts  uart4uart4-xfer h<uart4-cts  uart4-rts  tsadcotp-gpio  hBotp-out  hCpwm0pwm0-pin hNpwm1pwm1-pin hOpwm2pwm2-pin hPpwm3pwm3-pin hQgmacrgmii-pins  rmii-pins spdifspdif-tx  hcpcfg-pull-none-drv-8ma < Ihpcfg-pull-up-drv-8ma  Ipcfg-output-high Xhbuttonspwr-key-l hap-lid-int-l hpwr-key-h hpmicpmic-int-l hIrebootap-warm-reset-h  hrecovery-switchrec-mode-l  tpmtpm-int-h write-protectfw-wp-ap codechp-det hint-codec hMmic-det  hheadsetts3a227e-int-l h2backlightbl-en hchargerac-present-ap hcros-ecec-int h%suspendsuspend-l-wake hsuspend-l-sleep htrackpadtrackpad-int h3usb-hosthost1-pwr-en  husbotg-pwren-h  hchosen dserial2:115200n8memorymemorybt-activity gpio-keysdefault(bt-wake pBT Wakeup  vpower-button gpio-keysdefault(power pPower 1 vt dgpio-restart gpio-restart 1 default( sdio-pwrseqmmc-pwrseq-simple; ext_clockdefault( hvcc-5vregulator-fixedQvcc_5v`tLK@LK@ hJvcc33-sysregulator-fixed Qvcc33_sys`t2Z2Z hvcc50-hdmiregulator-fixed Qvcc50_hdmi`t Jvdd-logicpwm-regulator Qvdd_logic   { `t~psound!rockchip,rockchip-audio-max98090default( VEYRON-I2S   &L <L  Sbacklightpwm-backlight j  !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~ | default( B@  hpanelinnolux,n116bgesimple-panelokay ` panel-timingl V  <     ,  8  Bportsportendpoint hxgpio-charger gpio-charger Omains 1default(lid-switch gpio-keysdefault(lid pLid 1 v \ power 1vccsysregulator-fixedQvccsyst`hvcc5-host1-regulatorregulator-fixed m 1 default( Qvcc5_host1`tvcc5v-otg-regulatorregulator-fixed m 1 default( Qvcc5_host2`t #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2i2c20interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendportsmax-frequencyfifo-depthreset-namesbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaycd-gpiosrockchip,default-sample-phasesd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplypinctrl-namespinctrl-0wp-gpioscap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removabledisable-wpmmc-hs200-1_8v#io-channel-cellsdmasdma-namesgoogle,cros-ec-spi-pre-delayspi-max-frequencygoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countkeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymaprx-sample-delay-nsi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedti,micbiasvcc-supplywakeup-sourcereg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphysphy-namesneeds-reset-on-resumedr_modesnps,reset-phy-on-wakesnps,need-phy-for-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeassigned-clocksassigned-clock-parentsrockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc12-supplyvddio-supplyvcc10-supplyvcc9-supplyvcc11-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supplyaudio-supplysdcard-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointforce-hpdmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathlabellinux,codedebounce-intervalpriorityreset-gpiosvin-supplypwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unitrockchip,modelrockchip,i2s-controllerrockchip,audio-codecrockchip,hp-det-gpiosrockchip,mic-det-gpiosrockchip,headset-codecbrightness-levelsdefault-brightness-levelenable-gpiospost-pwm-on-delay-mspwm-off-delay-mspower-supplybacklighthactivehfront-porchhback-porchhsync-lenhsync-activevactivevfront-porchvback-porchvsync-lenvsync-activecharger-typelinux,input-typeenable-active-highgpio