K8E(E,Hardkernel ODROID-C1%2hardkernel,odroid-c1amlogic,meson8bcache-controller@c42000002arm,pl310-cache= AO [ l| soc 2simple-buscbus@c1100000 2simple-bus=   system-controller@4000,2amlogic,meson-hhi-sysctrlsimple-mfdsyscon=@ clock-controller2amlogic,meson8b-clkc  xtalddr_pllpower-controller2amlogic,meson8b-pwrcXBCKO F"dblkpic_dchdmi_apbhdmi_systemvencivencpvdacvenclviuvencrdmavpu.> Gassist@7c002amlogic,meson-mx-assistsyscon=|rng@8100&2amlogic,meson8b-rngamlogic,meson-rng=coreserial@84c0(2amlogic,meson8b-uartamlogic,meson-uart= S ^disabled baudxtalpclkserial@84dc(2amlogic,meson8b-uartamlogic,meson-uart= SK ^disabled 0baudxtalpclki2c@85002amlogic,meson6-i2c=  S ^disabledpwm@85502amlogic,meson8b-pwm=Pe ^disabledpwm@86502amlogic,meson8b-pwm=Pe^okaypzdefaultclkin0clkin1,adc@8680,2amlogic,meson8b-saradcamlogic,meson-saradc=4 SI^okay  clkincore  temperature_calib *serial@8700(2amlogic,meson8b-uartamlogic,meson-uart= S] ^disabled Dbaudxtalpclki2c@87c02amlogic,meson6-i2c=  S ^disabledphy@880032amlogic,meson8b-usb2-phyamlogic,meson-mx-usb2-phy=  ^disabled72usb_generalusb"phy@882032amlogic,meson8b-usb2-phyamlogic,meson-mx-usb2-phy= ^okay73usb_generalusb"mmc@8c20+2amlogic,meson8b-sdioamlogic,meson-mx-sdio=  S^okay  coreclkinp zdefaultslot@1 2mmc-slot=^okay " 5+7spi@8c802amlogic,meson6-spifc= ^disabledmmc@8e00*2amlogic,meson8-sdhcamlogic,meson-mx-sdhc=B SN^okay$!clkin0clkin1clkin2clkin3pclkpzdefaultDRa+7 interrupt-controller@988022amlogic,meson-gpio-intcamlogic,meson8b-gpio-intc=l @ABCDEFG^okaywatchdog@99002amlogic,meson8b-wdt= Stimer@99402amlogic,meson6-timer=@0S     xtalpclkreset-controller@44042amlogic,meson8b-reset=Danalog-top@81a8"2amlogic,meson8b-analog-topsyscon=pwm@86c02amlogic,meson8b-pwm=e ^disabledclock-measure@87582amlogic,meson8b-clk-measure=Xpinctrl@98802amlogic,meson8b-cbus-pinctrl=banks@80b0 =( 08muxpullpull-enablegpioSJ2 Header Pin 35J2 Header Pin 36J2 Header Pin 32J2 Header Pin 31J2 Header Pin 29J2 Header Pin 18J2 Header Pin 22J2 Header Pin 16J2 Header Pin 23J2 Header Pin 21J2 Header Pin 19J2 Header Pin 33J2 Header Pin 8J2 Header Pin 10J2 Header Pin 15J2 Header Pin 13J2 Header Pin 24J2 Header Pin 26Revision (upper)Revision (lower)J2 Header Pin 7J2 Header Pin 12J2 Header Pin 11TFLASH_VDD_ENVCCK_PWM (PWM_C)I2CA_SDAI2CA_SCLI2CB_SDAI2CB_SCLVDDEE_PWM (PWM_D)HDMI_HPDHDMI_I2C_SDAHDMI_I2C_SCLETH_PHY_INTRETH_PHY_NRSTETH_TXD1ETH_TXD0ETH_TXD3ETH_TXD2ETH_RGMII_TX_CLKSD_DATA1 (SDB_D1)SD_DATA0 (SDB_D0)SD_CLKSD_CMDSD_DATA3 (SDB_D3)SD_DATA2 (SDB_D2)SD_CDN (SD_DET_N)SDC_D0 (EMMC)SDC_D1 (EMMC)SDC_D2 (EMMC)SDC_D3 (EMMC)SDC_D4 (EMMC)SDC_D5 (EMMC)SDC_D6 (EMMC)SDC_D7 (EMMC)SDC_CLK (EMMC)SDC_RSTn (EMMC)SDC_CMD (EMMC)BOOT_SELETH_RXD1ETH_RXD0ETH_RX_DVRGMII_RX_CLKETH_RXD3ETH_RXD2ETH_TXENETH_PHY_REF_CLK_25MOUTETH_MDCETH_MDIO eth-rgmiimuxeth_tx_clketh_tx_eneth_txd1_0eth_txd0_0eth_rx_clketh_rx_dveth_rxd1eth_rxd0eth_mdio_eneth_mdceth_ref_clketh_txd2eth_txd3eth_rxd3eth_rxd2 etherneteth-rmiimux[eth_tx_eneth_txd1_0eth_txd0_0eth_rx_clketh_rx_dveth_rxd1eth_rxd0eth_mdio_eneth_mdc etherneti2c-amuxi2c_sda_ai2c_sck_ai2c_asd-b mux2sd_d0_bsd_d1_bsd_d2_bsd_d3_bsd_clk_bsd_cmd_bsd_bsdxc-cmux6sdxc_d0_csdxc_d13_csdxc_d47_csdxc_clk_csdxc_cmd_csdxc_c pwm-c1muxpwm_c1pwm_cpwm-dmuxpwm_dpwm_duart-b0muxuart_tx_b0uart_rx_b0uart_buart-b0-cts-rtsmuxuart_cts_b0uart_rts_b0uart_bbus@c4300000 2simple-bus=0 0interrupt-controller@10002arm,cortex-a9-gic=lscu@02arm,cortex-a5-scu=timer@2002arm,cortex-a5-global-timer=  S ~ ^disabledtimer@6002arm,cortex-a5-twd-timer=  S ~aobus@c8100000 2simple-bus= ir-receiver@4802amlogic,meson6-ir=  S^okaypzdefaultserial@4c0(2amlogic,meson8b-uartamlogic,meson-uart= SZ^okay  baudxtalpclkpzdefaulti2c@5002amlogic,meson6-i2c=  S\ ^disabled rtc@7402amlogic,meson8b-rtc=@ SH ^disabledpmu@e02amlogic,meson8b-pmusyscon=pinctrl@842amlogic,meson8b-aobus-pinctrl= ao-bank@14=,$muxpullgpioUART TXUART RXTF_3V3N_1V8_ENUSB_HUB_RST_NUSB_OTG_PWRENJ7 Header Pin 2IR_INJ7 Header Pin 4J7 Header Pin 6J7 Header Pin 5J7 Header Pin 7HDMI_CECSYS_LED)usb-hub$%-9usb-hub-resetuart_ao_amuxuart_tx_ao_auart_rx_ao_auart_aoremotemux remote_inputremoteusb@c90400002amlogic,meson8b-usbsnps,dwc2= SC Husb2-phyRashost ^disabledAotgusb@c90c00002amlogic,meson8b-usbsnps,dwc2=  SC Husb2-phyhost^okay@otgethernet@c941000022amlogic,meson8b-dwmacsnps,dwmac-3.70asnps,dwmac=A@ Smacirq^okay $__*stmmacethclkin0clkin1timing-adjustment+ "stmmacethpzdefault rgmii-id mac-addressmdio2snps,dwmac-mdioethernet-phy@0='u0  )Ssram@d9000000 2mmio-sram= smp-sram@1ff802amlogic,meson8b-smp-sram=bootrom@d9040000 2amlogic,meson-mx-bootromsyscon=secbus@da000000 2simple-bus=` `nvmem@02amlogic,meson8b-efuse= :corecalib@1f4= mac@1b4=xtal-clk 2fixed-clockn6xtalcpuscpu@200)cpu2arm,cortex-a55 =Famlogic,meson8b-smpT! h"#cpu@201)cpu2arm,cortex-a55 =Famlogic,meson8b-smpT! $cpu@202)cpu2arm,cortex-a55 =Famlogic,meson8b-smpT! %cpu@203)cpu2arm,cortex-a55 =Famlogic,meson8b-smpT! &opp-table2operating-points-v2s!opp-96000000~ `opp-192000000~ q `opp-312000000~ `opp-408000000~Q `opp-504000000~ n `opp-600000000~#F `opp-720000000~*T `opp-816000000~0, opp-1008000000~<e opp-1200000000~Ge opp-1320000000~Ne opp-1488000000~Xe opp-1536000000~[e gpu-opp-table2operating-points-v2'opp-255000000~2opp-364285714~opp-425000000~T@opp-510000000~eopp-637500000~%z`pmu2arm,cortex-a5-pmu0S#$%&reserved-memoryhwrom@0= bus@c8000000 2simple-bus= clock-controller@4002amlogic,meson8b-ddr-clkc= xtalbus@6000 2simple-bus=` `video-lut@48&2amlogic,meson8b-canvasamlogic,canvas=Hbus@d0000000 2simple-bus=  gpu@c0000"2amlogic,meson8b-maliarm,mali-450= `S&gpgpmmupppmupp0ppmmu0pp1ppmmu1N   buscoreT'(aliases/soc/aobus@c8100000/serial@4c0#/soc/cbus@c1100000/mmc@8c20/slot@1/soc/cbus@c1100000/mmc@8e00chosenserial0:115200n8memory)memory=@@emmc-pwrseq2mmc-pwrseq-emmc  ?leds 2gpio-ledsbluec1:blue:alive %)  heartbeatoffregulator-p5v02regulator-fixed P5V0LK@3LK@+regulator-tflash_vdd2regulator-fixed  TFLASH_VDD2Z32ZK V [gpio-regulator-tf_io2regulator-gpio TF_IOw@32ZK %)nt2Zw@iio-hwmon 2iio-hwmon{*rtc32k-xtal-clk 2fixed-clockRTC32Kregulator-vcc-1v82regulator-fixed VCC1V8w@3w@K+ regulator-vcc-3v32regulator-fixed VCC3V32Z32ZK+regulator-vcck2pwm-regulator VCCK `3e K+,/["regulator-vddc-ddr2regulator-fixed  DDR_VDDC`3`K+regulator-vddee2pwm-regulator VDDEE `3e K+,/[(regulator-vdd-rtc2regulator-fixed VDD_RTC 3 K #address-cells#size-cellsinterrupt-parentmodelcompatibleregcache-unifiedcache-levelarm,data-latencyarm,tag-latencyarm,filter-rangesprefetch-dataprefetch-instrarm,shared-overridephandleclocksclock-names#clock-cells#reset-cells#power-domain-cellsamlogic,ao-sysctrlresetsreset-namesassigned-clocksassigned-clock-ratesinterruptsstatus#pwm-cellspinctrl-0pinctrl-names#io-channel-cellsamlogic,hhi-sysctrlnvmem-cellsnvmem-cell-namesvref-supply#phy-cellsbus-widthno-sdiocap-mmc-highspeedcap-sd-highspeeddisable-wpcd-gpiosvmmc-supplyvqmmc-supplymax-frequencymmc-hs200-1_8vmmc-pwrseqinterrupt-controller#interrupt-cellsamlogic,channel-interruptsreg-namesgpio-controller#gpio-cellsgpio-rangesgpio-line-namesgroupsfunctionbias-disablebias-pull-upvdd-supplygpio-hogoutput-highline-namephysphy-namesg-rx-fifo-sizeg-np-tx-fifo-sizeg-tx-fifo-sizedr_modeinterrupt-namesrx-fifo-depthtx-fifo-depthpower-domainsphy-handlephy-modereset-assert-usreset-deassert-usreset-gpiosclock-frequencyclock-output-namesdevice_typenext-level-cacheenable-methodoperating-points-v2cpu-supplyopp-sharedopp-hzopp-microvoltturbo-modeinterrupt-affinityno-mapmali-supplyserial0mmc0mmc1stdout-pathlabellinux,default-triggerdefault-stateregulator-nameregulator-min-microvoltregulator-max-microvoltvin-supplygpioenable-active-highgpios-statesio-channelspwmspwm-dutycycle-rangeregulator-boot-onregulator-always-on