8,( ,timll,omap3-devkit8000ti,omap3430ti,omap3 +7TimLL OMAP3 Devkit8000chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000 d/connector0 m/connector1cpus+cpu@0arm,cortex-a8vcpucpupmu@54000000arm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bush +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus + pinmux@30 ti,omap3-padconfpinctrl-single08+ *pinmux_twl4030_pinsGA[pinmux_dss_dpi_pinsG[scm_conf@270sysconsimple-busp0+ p0[pbias_regulator@2b0ti,pbias-omap3ti,pbias-omapcpbias_mmc_omap2430jpbias_mmc_omap2430yw@-[clocks+mcbsp5_mux_fck@68ti,composite-mux-clockh[mcbsp5_fckti,composite-clock[mcbsp1_mux_fck@4ti,composite-mux-clock[ mcbsp1_fckti,composite-clock [mcbsp2_mux_fck@4ti,composite-mux-clock [ mcbsp2_fckti,composite-clock [mcbsp3_mux_fck@68ti,composite-mux-clock h[mcbsp3_fckti,composite-clock[mcbsp4_mux_fck@68ti,composite-mux-clock h[mcbsp4_fckti,composite-clock[clockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \+ *pinmux_twl4030_vpins G[target-module@480a6000ti,sysc-omap2ti,syscH `DH `HH `Lrevsyscsyss ick+ H ` aes1@0 ti,omap3-aesP  txrxtarget-module@480c5000ti,sysc-omap2ti,syscH PDH PHH PLrevsyscsyss ick+ H P aes2@0 ti,omap3-aesPABtxrxprm@48306000 ti,omap3-prmH0`@ clocks+virt_16_8m_ck fixed-clockY[osc_sys_ck@d40 ti,mux-clock @[sys_ck@1270ti,divider-clockp[ sys_clkout1@d70ti,gate-clock pdpll3_x2_ckfixed-factor-clock6Adpll3_m2x2_ckfixed-factor-clock6A[dpll4_x2_ckfixed-factor-clock6Acorex2_fckfixed-factor-clock6A[!wkup_l4_ickfixed-factor-clock 6A[Pcorex2_d3_fckfixed-factor-clock!6A[corex2_d5_fckfixed-factor-clock!6A[clockdomainscm@48004000 ti,omap3-cmH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clock[Bvirt_12m_ck fixed-clock[virt_13m_ck fixed-clock]@[virt_19200000_ck fixed-clock$[virt_26000000_ck fixed-clock[virt_38_4m_ck fixed-clockI[dpll4_ck@d00ti,omap3-dpll-per-clock  D 0[dpll4_m2_ck@d48ti,divider-clock? H["dpll4_m2x2_mul_ckfixed-factor-clock"6A[#dpll4_m2x2_ck@d00ti,gate-clock# K[$omap_96m_alwon_fckfixed-factor-clock$6A[+dpll3_ck@d00ti,omap3-dpll-core-clock  @ 0[dpll3_m3_ck@1140ti,divider-clock@[%dpll3_m3x2_mul_ckfixed-factor-clock%6A[&dpll3_m3x2_ck@d00ti,gate-clock&  K['emu_core_alwon_ckfixed-factor-clock'6A[dsys_altclk fixed-clock[0mcbsp_clks fixed-clock[dpll3_m2_ck@d40ti,divider-clock @[core_ckfixed-factor-clock6A[(dpll1_fck@940ti,divider-clock( @[)dpll1_ck@904ti,omap3-dpll-clock )  $ @ 4[dpll1_x2_ckfixed-factor-clock6A[*dpll1_x2m2_ck@944ti,divider-clock* D[>cm_96m_fckfixed-factor-clock+6A[,omap_96m_fck@d40 ti,mux-clock,  @[Gdpll4_m3_ck@e40ti,divider-clock @[-dpll4_m3x2_mul_ckfixed-factor-clock-6A[.dpll4_m3x2_ck@d00ti,gate-clock. K[/omap_54m_fck@d40 ti,mux-clock/0 @[:cm_96m_d2_fckfixed-factor-clock,6A[1omap_48m_fck@d40 ti,mux-clock10 @[2omap_12m_fckfixed-factor-clock26A[Idpll4_m4_ck@e40ti,divider-clock@[3dpll4_m4x2_mul_ckti,fixed-factor-clock3ao|[4dpll4_m4x2_ck@d00ti,gate-clock4 K|[dpll4_m5_ck@f40ti,divider-clock?@[5dpll4_m5x2_mul_ckti,fixed-factor-clock5ao|[6dpll4_m5x2_ck@d00ti,gate-clock6 K|[ldpll4_m6_ck@1140ti,divider-clock?@[7dpll4_m6x2_mul_ckfixed-factor-clock76A[8dpll4_m6x2_ck@d00ti,gate-clock8 K[9emu_per_alwon_ckfixed-factor-clock96A[eclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock( p[;clkout2_src_mux_ck@d70ti,composite-mux-clock( ,: p[<clkout2_src_ckti,composite-clock;<[=sys_clkout2@d70ti,divider-clock=@ pmpu_ckfixed-factor-clock>6A[?arm_fck@924ti,divider-clock? $emu_mpu_alwon_ckfixed-factor-clock?6A[fl3_ick@a40ti,divider-clock( @[@l4_ick@a40ti,divider-clock@ @[Arm_ick@c40ti,divider-clockA @gpt10_gate_fck@a00ti,composite-gate-clock   [Cgpt10_mux_fck@a40ti,composite-mux-clockB  @[Dgpt10_fckti,composite-clockCDgpt11_gate_fck@a00ti,composite-gate-clock   [Egpt11_mux_fck@a40ti,composite-mux-clockB  @[Fgpt11_fckti,composite-clockEFcore_96m_fckfixed-factor-clockG6A[mmchs2_fck@a00ti,wait-gate-clock [mmchs1_fck@a00ti,wait-gate-clock [i2c3_fck@a00ti,wait-gate-clock [i2c2_fck@a00ti,wait-gate-clock [i2c1_fck@a00ti,wait-gate-clock [mcbsp5_gate_fck@a00ti,composite-gate-clock  [mcbsp1_gate_fck@a00ti,composite-gate-clock  [ core_48m_fckfixed-factor-clock26A[Hmcspi4_fck@a00ti,wait-gate-clockH [mcspi3_fck@a00ti,wait-gate-clockH [mcspi2_fck@a00ti,wait-gate-clockH [mcspi1_fck@a00ti,wait-gate-clockH [uart2_fck@a00ti,wait-gate-clockH [uart1_fck@a00ti,wait-gate-clockH  [core_12m_fckfixed-factor-clockI6A[Jhdq_fck@a00ti,wait-gate-clockJ [core_l3_ickfixed-factor-clock@6A[Ksdrc_ick@a10ti,wait-gate-clockK [gpmc_fckfixed-factor-clockK6Acore_l4_ickfixed-factor-clockA6A[Lmmchs2_ick@a10ti,omap3-interface-clockL [mmchs1_ick@a10ti,omap3-interface-clockL [hdq_ick@a10ti,omap3-interface-clockL [mcspi4_ick@a10ti,omap3-interface-clockL [mcspi3_ick@a10ti,omap3-interface-clockL [mcspi2_ick@a10ti,omap3-interface-clockL [mcspi1_ick@a10ti,omap3-interface-clockL [i2c3_ick@a10ti,omap3-interface-clockL [i2c2_ick@a10ti,omap3-interface-clockL [i2c1_ick@a10ti,omap3-interface-clockL [uart2_ick@a10ti,omap3-interface-clockL [uart1_ick@a10ti,omap3-interface-clockL  [gpt11_ick@a10ti,omap3-interface-clockL  [gpt10_ick@a10ti,omap3-interface-clockL  [mcbsp5_ick@a10ti,omap3-interface-clockL  [mcbsp1_ick@a10ti,omap3-interface-clockL  [omapctrl_ick@a10ti,omap3-interface-clockL [dss_tv_fck@e00ti,gate-clock:[dss_96m_fck@e00ti,gate-clockG[dss2_alwon_fck@e00ti,gate-clock [dummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock  [Mgpt1_mux_fck@c40ti,composite-mux-clockB  @[Ngpt1_fckti,composite-clockMN[aes2_ick@a10ti,omap3-interface-clockL [wkup_32k_fckfixed-factor-clockB6A[Ogpio1_dbck@c00ti,gate-clockO [sha12_ick@a10ti,omap3-interface-clockL [wdt2_fck@c00ti,wait-gate-clockO [wdt2_ick@c10ti,omap3-interface-clockP [wdt1_ick@c10ti,omap3-interface-clockP [gpio1_ick@c10ti,omap3-interface-clockP [omap_32ksync_ick@c10ti,omap3-interface-clockP [gpt12_ick@c10ti,omap3-interface-clockP [gpt1_ick@c10ti,omap3-interface-clockP [per_96m_fckfixed-factor-clock+6A[ per_48m_fckfixed-factor-clock26A[Quart3_fck@1000ti,wait-gate-clockQ [gpt2_gate_fck@1000ti,composite-gate-clock [Rgpt2_mux_fck@1040ti,composite-mux-clockB @[Sgpt2_fckti,composite-clockRS[gpt3_gate_fck@1000ti,composite-gate-clock [Tgpt3_mux_fck@1040ti,composite-mux-clockB @[Ugpt3_fckti,composite-clockTUgpt4_gate_fck@1000ti,composite-gate-clock [Vgpt4_mux_fck@1040ti,composite-mux-clockB @[Wgpt4_fckti,composite-clockVWgpt5_gate_fck@1000ti,composite-gate-clock [Xgpt5_mux_fck@1040ti,composite-mux-clockB @[Ygpt5_fckti,composite-clockXYgpt6_gate_fck@1000ti,composite-gate-clock [Zgpt6_mux_fck@1040ti,composite-mux-clockB @[[gpt6_fckti,composite-clockZ[gpt7_gate_fck@1000ti,composite-gate-clock [\gpt7_mux_fck@1040ti,composite-mux-clockB @[]gpt7_fckti,composite-clock\]gpt8_gate_fck@1000ti,composite-gate-clock  [^gpt8_mux_fck@1040ti,composite-mux-clockB @[_gpt8_fckti,composite-clock^_gpt9_gate_fck@1000ti,composite-gate-clock  [`gpt9_mux_fck@1040ti,composite-mux-clockB @[agpt9_fckti,composite-clock`aper_32k_alwon_fckfixed-factor-clockB6A[bgpio6_dbck@1000ti,gate-clockb[gpio5_dbck@1000ti,gate-clockb[gpio4_dbck@1000ti,gate-clockb[gpio3_dbck@1000ti,gate-clockb[gpio2_dbck@1000ti,gate-clockb [wdt3_fck@1000ti,wait-gate-clockb [per_l4_ickfixed-factor-clockA6A[cgpio6_ick@1010ti,omap3-interface-clockc[gpio5_ick@1010ti,omap3-interface-clockc[gpio4_ick@1010ti,omap3-interface-clockc[gpio3_ick@1010ti,omap3-interface-clockc[gpio2_ick@1010ti,omap3-interface-clockc [wdt3_ick@1010ti,omap3-interface-clockc [uart3_ick@1010ti,omap3-interface-clockc [uart4_ick@1010ti,omap3-interface-clockc[gpt9_ick@1010ti,omap3-interface-clockc [gpt8_ick@1010ti,omap3-interface-clockc [gpt7_ick@1010ti,omap3-interface-clockc[gpt6_ick@1010ti,omap3-interface-clockc[gpt5_ick@1010ti,omap3-interface-clockc[gpt4_ick@1010ti,omap3-interface-clockc[gpt3_ick@1010ti,omap3-interface-clockc[gpt2_ick@1010ti,omap3-interface-clockc[mcbsp2_ick@1010ti,omap3-interface-clockc[mcbsp3_ick@1010ti,omap3-interface-clockc[mcbsp4_ick@1010ti,omap3-interface-clockc[mcbsp2_gate_fck@1000ti,composite-gate-clock[ mcbsp3_gate_fck@1000ti,composite-gate-clock[mcbsp4_gate_fck@1000ti,composite-gate-clock[emu_src_mux_ck@1140 ti,mux-clock def@[gemu_src_ckti,clkdm-gate-clockg[hpclk_fck@1140ti,divider-clockh@pclkx2_fck@1140ti,divider-clockh@atclk_fck@1140ti,divider-clockh@traceclk_src_fck@1140 ti,mux-clock def@[itraceclk_fck@1140ti,divider-clocki @secure_32k_fck fixed-clock[jgpt12_fckfixed-factor-clockj6A[wdt1_fckfixed-factor-clockj6Asecurity_l4_ick2fixed-factor-clockA6A[kaes1_ick@a14ti,omap3-interface-clockk [rng_ick@a14ti,omap3-interface-clockk [sha11_ick@a14ti,omap3-interface-clockk des1_ick@a14ti,omap3-interface-clockk cam_mclk@f00ti,gate-clockl|cam_ick@f10!ti,omap3-no-wait-interface-clockA[csi2_96m_fck@f00ti,gate-clock[security_l3_ickfixed-factor-clock@6A[mpka_ick@a14ti,omap3-interface-clockm icr_ick@a10ti,omap3-interface-clockL des2_ick@a10ti,omap3-interface-clockL mspro_ick@a10ti,omap3-interface-clockL mailboxes_ick@a10ti,omap3-interface-clockL ssi_l4_ickfixed-factor-clockA6A[tsr1_fck@c00ti,wait-gate-clock  [sr2_fck@c00ti,wait-gate-clock  [sr_l4_ickfixed-factor-clockA6Adpll2_fck@40ti,divider-clock(@[ndpll2_ck@4ti,omap3-dpll-clock n$@4[odpll2_m2_ck@44ti,divider-clockoD[piva2_ck@0ti,wait-gate-clockp[modem_fck@a00ti,omap3-interface-clock  [sad2d_ick@a10ti,omap3-interface-clock@ [mad2d_ick@a18ti,omap3-interface-clock@ [mspro_fck@a00ti,wait-gate-clock ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock! [qssi_ssr_div_fck_3430es2@a40ti,composite-divider-clock! @$[rssi_ssr_fck_3430es2ti,composite-clockqr[sssi_sst_fck_3430es2fixed-factor-clocks6A[hsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clockK [ssi_ick_3430es2@a10ti,omap3-ssi-interface-clockt [usim_gate_fck@c00ti,composite-gate-clockG  [sys_d2_ckfixed-factor-clock 6A[vomap_96m_d2_fckfixed-factor-clockG6A[womap_96m_d4_fckfixed-factor-clockG6A[xomap_96m_d8_fckfixed-factor-clockG6A[yomap_96m_d10_fckfixed-factor-clockG6A [zdpll5_m2_d4_ckfixed-factor-clocku6A[{dpll5_m2_d8_ckfixed-factor-clocku6A[|dpll5_m2_d16_ckfixed-factor-clocku6A[}dpll5_m2_d20_ckfixed-factor-clocku6A[~usim_mux_fck@c40ti,composite-mux-clock( vwxyz{|}~ @[usim_fckti,composite-clockusim_ick@c10ti,omap3-interface-clockP  [dpll5_ck@d04ti,omap3-dpll-clock   $ L 4[dpll5_m2_ck@d50ti,divider-clock P[usgx_gate_fck@b00ti,composite-gate-clock( [core_d3_ckfixed-factor-clock(6A[core_d4_ckfixed-factor-clock(6A[core_d6_ckfixed-factor-clock(6A[omap_192m_alwon_fckfixed-factor-clock$6A[core_d2_ckfixed-factor-clock(6A[sgx_mux_fck@b40ti,composite-mux-clock , @[sgx_fckti,composite-clock[sgx_ick@b10ti,wait-gate-clock@ [cpefuse_fck@a08ti,gate-clock  [ts_fck@a08ti,gate-clockB [usbtll_fck@a08ti,wait-gate-clocku [usbtll_ick@a18ti,omap3-interface-clockL [mmchs3_ick@a10ti,omap3-interface-clockL [mmchs3_fck@a00ti,wait-gate-clock [dss1_alwon_fck_3430es2@e00ti,dss-gate-clock|[dss_ick_3430es2@e10ti,omap3-dss-interface-clockA[usbhost_120m_fck@1400ti,gate-clocku[usbhost_48m_fck@1400ti,dss-gate-clock2[usbhost_ick@1410ti,omap3-dss-interface-clockA[clockdomainscore_l3_clkdmti,clockdomaindpll3_clkdmti,clockdomaindpll1_clkdmti,clockdomainper_clkdmti,clockdomainhemu_clkdmti,clockdomainhdpll4_clkdmti,clockdomainwkup_clkdmti,clockdomain$dss_clkdmti,clockdomaincore_l4_clkdmti,clockdomaincam_clkdmti,clockdomainiva2_clkdmti,clockdomaindpll2_clkdmti,clockdomainod2d_clkdmti,clockdomain dpll5_clkdmti,clockdomainsgx_clkdmti,clockdomainusbhost_clkdmti,clockdomain target-module@48320000ti,sysc-omap2ti,syscH2H2 revsyscOfckick+ H2counter@0ti,omap-counter32k  disabledinterrupt-controller@48200000ti,omap3-intcH [target-module@48056000ti,sysc-omap2ti,syscH`H`,H`(revsyscsyss#  Kick+ H`dma-controller@0ti,omap3430-sdmati,omap-sdma   `[gpio@48310000ti,omap3-gpioH1gpio1+;[gpio@49050000ti,omap3-gpioIgpio2+;gpio@49052000ti,omap3-gpioI gpio3+;gpio@49054000ti,omap3-gpioI@ gpio4+;gpio@49056000ti,omap3-gpioI`!gpio5+;gpio@49058000ti,omap3-gpioI"gpio6+;[serial@4806a000ti,omap3-uartH GH12txrxuart1lserial@4806c000ti,omap3-uartHGI34txrxuart2lserial@49020000ti,omap3-uartIGJ56txrxuart3li2c@48070000 ti,omap3-i2cH8txrx+i2c1'@twl@48H ti,twl4030[defaultiaudioti,twl4030-audiocodecrtcti,twl4030-rtc bciti,twl4030-bci s vacwatchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1y ' regulator-vdacti,twl4030-vdacyw@w@[regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1y:0[regulator-vmmc2ti,twl4030-vmmc2y:0regulator-vusb1v5ti,twl4030-vusb1v5[regulator-vusb1v8ti,twl4030-vusb1v8[regulator-vusb3v1ti,twl4030-vusb3v1[regulator-vpll1ti,twl4030-vpll1 jvdds_dsiyw@w@[regulator-vpll2ti,twl4030-vpll2yw@w@regulator-vsimti,twl4030-vsimyw@-[gpioti,twl4030-gpio+;[twl4030-usbti,twl4030-usb pwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypadD#?  @A Bsrmadcti,twl4030-madc0[i2c@48072000 ti,omap3-i2cH 9txrx+i2c2[ i2c@48060000 ti,omap3-i2cH=txrx+i2c3 disabledmailbox@48094000ti,omap3-mailboxmailboxH @BN`dsp r }spi@48098000ti,omap2-mcspiH A+mcspi1@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap2-mcspiH B+mcspi2 +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiH [+mcspi3 tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiH 0+mcspi4FGtx0rx01w@480b2000 ti,omap3-1wH :hdq1wmmc@4809c000ti,omap3-hsmmcH Smmc1=>txrxmmc@480b4000ti,omap3-hsmmcH @Vmmc2/0txrx disabledmmc@480ad000ti,omap3-hsmmcH ^mmc3MNtxrx disabledmmu@480bd400ti,omap2-iommuH mmu_isp[mmu@5d000000ti,omap2-iommu]mmu_iva disabledwdt@48314000 ti,omap3-wdtH1@ wd_timer2 disabledmcbsp@48074000ti,omap3-mcbspH@mpu ;< commontxrxmcbsp1 txrxfck disabledtarget-module@480a0000ti,sysc-omap2ti,syscH <H @H Drevsyscsyssick+ H rng@0 ti,omap2-rng 4mcbsp@49022000ti,omap3-mcbspI I mpusidetone>?commontxrxsidetonemcbsp2mcbsp2_sidetone!"txrxfckickokay[mcbsp@49024000ti,omap3-mcbspI@I mpusidetoneYZcommontxrxsidetonemcbsp3mcbsp3_sidetonetxrxfckick disabledmcbsp@49026000ti,omap3-mcbspI`mpu 67 commontxrxmcbsp4txrxfck disabledmcbsp@48096000ti,omap3-mcbspH `mpu QR commontxrxmcbsp5txrxfck disabledsham@480c3000ti,omap3-shamshamH 0d1Erxtarget-module@48318000ti,sysc-omap2-timerti,syscH1H1H1revsyscsyss' fckick+ H1timer@0ti,omap3430-timerfck% 0Btarget-module@49032000ti,sysc-omap2-timerti,syscI I I revsyscsyss' fckick+ I G[timer@0ti,omap3430-timer& 0 timer@49034000ti,omap3430-timerI@'timer3timer@49036000ti,omap3430-timerI`(timer4timer@49038000ti,omap3430-timerI)timer5ftimer@4903a000ti,omap3430-timerI*timer6ftimer@4903c000ti,omap3430-timerI+timer7ftimer@4903e000ti,omap3430-timerI,timer8sftimer@49040000ti,omap3430-timerI-timer9stimer@48086000ti,omap3430-timerH`.timer10stimer@48088000ti,omap3430-timerH/timer11starget-module@48304000ti,sysc-omap2-timerti,syscH0@H0@H0@revsyscsyss' fckick+ H0@G[timer@0ti,omap3430-timer_usbhstll@48062000 ti,usbhs-tllH N usb_tll_hsusbhshost@48064000ti,usbhs-hostH@ usb_host_hs+ohci@48064400ti,ohci-omap3HDLehci@48064800 ti,ehci-omapHHMgpmc@6e000000ti,omap3430-gpmcgpmcnrxtx++; 0,[nand@0,0ti,omap2-nand  sw%,7,IX"k,~(6@RR(+x-loader@0 X-Loaderbootloaders@80000U-Bootbootloaders_env@260000 U-Boot Env&kernel@280000Kernel(@filesystem@680000 File Systemhethernet@6,0davicom,dm9000 ,:T%7IXk0n6|6~ZZusb_otg_hs@480ab000ti,omap3-musbH \]mcdma usb_otg_hs dss@48050000 ti,omap3-dssHok dss_corefck+[defaulti 0dispc@48050400ti,omap3-dispcH dss_dispcfckencoder@4804fc00 ti,omap3-dsiHH@H protophypll disabled dss_dsi1 fcksys_clkencoder@48050800ti,omap3-rfbiH disabled dss_rfbifckickencoder@48050c00ti,omap3-vencH ok dss_vencfck@portendpointL\[ port+endpoint@0Lh[endpoint@1ssi-controller@48058000 ti,omap3-ssissiokHHsysgddGgdd_mpu+ s ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portHHtxrxCDssi-port@4805b000ti,omap3-ssi-portHHtxrxEFpinmux@480025d8 ti,omap3-padconfpinctrl-singleH%$+ *isp@480bc000 ti,omap3-ispH H |sclzports+bandgap@48002524H%$ti,omap34xx-bandgap[target-module@480cb000ti,sysc-omap3430-srti,syscsmartreflex_coreH $syscfck+ H smartreflex@0ti,omap3-smartreflex-coretarget-module@480c9000ti,sysc-omap3430-srti,syscsmartreflex_mpu_ivaH $syscfck+ H smartreflex@480c9000ti,omap3-smartreflex-mpu-ivatarget-module@50000000ti,sysc-omap2ti,syscPrevfckick+ P@opp-tableoperating-points-v2-ti-cpuc[opp1-125000000sY@ opp2-250000000沀 g8g8g8opp3-500000000e OOOopp4-550000000 U txtxtxopp5-600000000#F pppopp6-720000000*T pppthermal-zonescpu_thermalN  memory@80000000vmemoryleds gpio-ledsheartbeatdevkit8000::led1  on .heartbeatmmcdevkit8000::led2  on .noneusrdevkit8000::led3  on .usrpmu_statdevkit8000::pmu_stat soundti,omap-twl4030 Ddevkit8000 MI VExt SpkPREDRIVELExt SpkPREDRIVERMAINMICMain MicMain MicMic Bias 1gpio_keys gpio-keysuseruser  g rencoder0 ti,tfp410 ports+port@0endpointL[port@1endpointL[ connector0dvi-connectordvi   portendpointL [connector1svideo-connectortvportendpointL [ compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2display1display2device_typeregclocksclock-namesclock-latencyoperating-points-v2interruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinsphandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftreg-namesti,sysc-maskti,sysc-sidleti,syss-maskdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersstatusti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0bci3v1-supplyio-channelsio-channel-namesti,use-ledsti,pulldownsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplyvqmmc-supplybus-width#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsassigned-clocksassigned-clock-parentsti,no-reset-on-initti,no-idleti,timer-dspti,timer-pwmti,timer-alwonti,timer-secureremote-wakeup-connectedgpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelbank-widthdavicom,no-eepromgpmc,mux-add-datagpmc,wait-pingpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,oe-on-nsgpmc,we-on-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsmultipointnum-epsram-bitsvdds_dsi-supplyvdda_dac-supplyvdda-supplyremote-endpointti,channelsdata-linesiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendturbo-modepolling-delay-passivepolling-delaycoefficientsthermal-sensorsgpiosdefault-statelinux,default-triggerti,modelti,mcbspti,audio-routinglinux,codewakeup-sourcepowerdown-gpiosdigitalddc-i2c-bus