8( "ti,omap3-evmti,omap3430ti,omap3 +7TI OMAP35XX EVM (TMDSEVM3530)chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000 d/displaycpus+cpu@0arm,cortex-a8mcpuy}cpupmu@54000000arm,cortex-a8-pmuyTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busyh +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-busy + pinmux@30 ti,omap3-padconfpinctrl-singley08+-JdefaultXbpinmux_twl4030_pinsjAbpinmux_dss_dpi_pins2jbpinmux_mmc1_pinsPj "$&bpinmux_mmc2_pinsPj(*,.02468:bpinmux_uart3_pinsjnApbpinmux_ehci_port_select_pinsjbpinmux_hsusb2_pins0j      bpinmux_wl12xx_gpiojPNbpinmux_smsc911x_pinsjbscm_conf@270sysconsimple-busyp0+ p0bpbias_regulator@2b0ti,pbias-omap3ti,pbias-omapy~pbias_mmc_omap2430pbias_mmc_omap2430w@-bclocks+mcbsp5_mux_fck@68ti,composite-mux-clock} yhb mcbsp5_fckti,composite-clock} bmcbsp1_mux_fck@4ti,composite-mux-clock} yb mcbsp1_fckti,composite-clock} bmcbsp2_mux_fck@4ti,composite-mux-clock} ybmcbsp2_fckti,composite-clock}bmcbsp3_mux_fck@68ti,composite-mux-clock} yhbmcbsp3_fckti,composite-clock}bmcbsp4_mux_fck@68ti,composite-mux-clock} yhbmcbsp4_fckti,composite-clock}bclockdomainspinmux@a00 ti,omap3-padconfpinctrl-singley \+-pinmux_twl4030_vpins jbpinmux_dss_dpi_pins10j  b target-module@480a6000ti,sysc-omap2ti,syscyH `DH `HH `Lrevsyscsyss }ick+ H ` aes1@0 ti,omap3-aesyP  txrxtarget-module@480c5000ti,sysc-omap2ti,syscyH PDH PHH PLrevsyscsyss }ick+ H P aes2@0 ti,omap3-aesyPABtxrxprm@48306000 ti,omap3-prmyH0`@ clocks+virt_16_8m_ck fixed-clockYbosc_sys_ck@d40 ti,mux-clock}y @bsys_ck@1270ti,divider-clock}/yp:b#sys_clkout1@d70ti,gate-clock}y pdpll3_x2_ckfixed-factor-clock}Q\dpll3_m2x2_ckfixed-factor-clock} Q\b"dpll4_x2_ckfixed-factor-clock}!Q\corex2_fckfixed-factor-clock}"Q\b$wkup_l4_ickfixed-factor-clock}#Q\bScorex2_d3_fckfixed-factor-clock}$Q\bcorex2_d5_fckfixed-factor-clock}$Q\bclockdomainscm@48004000 ti,omap3-cmyH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clockbEvirt_12m_ck fixed-clockbvirt_13m_ck fixed-clock]@bvirt_19200000_ck fixed-clock$bvirt_26000000_ck fixed-clockbvirt_38_4m_ck fixed-clockIbdpll4_ck@d00ti,omap3-dpll-per-clock}##y D 0b!dpll4_m2_ck@d48ti,divider-clock}!/?y H:b%dpll4_m2x2_mul_ckfixed-factor-clock}%Q\b&dpll4_m2x2_ck@d00ti,gate-clock}&y fb'omap_96m_alwon_fckfixed-factor-clock}'Q\b.dpll3_ck@d00ti,omap3-dpll-core-clock}##y @ 0bdpll3_m3_ck@1140ti,divider-clock}/y@:b(dpll3_m3x2_mul_ckfixed-factor-clock}(Q\b)dpll3_m3x2_ck@d00ti,gate-clock}) y fb*emu_core_alwon_ckfixed-factor-clock}*Q\bgsys_altclk fixed-clockb3mcbsp_clks fixed-clockb dpll3_m2_ck@d40ti,divider-clock}/y @:b core_ckfixed-factor-clock} Q\b+dpll1_fck@940ti,divider-clock}+/y @:b,dpll1_ck@904ti,omap3-dpll-clock}#,y  $ @ 4bdpll1_x2_ckfixed-factor-clock}Q\b-dpll1_x2m2_ck@944ti,divider-clock}-/y D:bAcm_96m_fckfixed-factor-clock}.Q\b/omap_96m_fck@d40 ti,mux-clock}/#y @bJdpll4_m3_ck@e40ti,divider-clock}!/ y@:b0dpll4_m3x2_mul_ckfixed-factor-clock}0Q\b1dpll4_m3x2_ck@d00ti,gate-clock}1y fb2omap_54m_fck@d40 ti,mux-clock}23y @b=cm_96m_d2_fckfixed-factor-clock}/Q\b4omap_48m_fck@d40 ti,mux-clock}43y @b5omap_12m_fckfixed-factor-clock}5Q\bLdpll4_m4_ck@e40ti,divider-clock}!/y@:b6dpll4_m4x2_mul_ckti,fixed-factor-clock}6|b7dpll4_m4x2_ck@d00ti,gate-clock}7y fbdpll4_m5_ck@f40ti,divider-clock}!/?y@:b8dpll4_m5x2_mul_ckti,fixed-factor-clock}8|b9dpll4_m5x2_ck@d00ti,gate-clock}9y fbodpll4_m6_ck@1140ti,divider-clock}!/?y@:b:dpll4_m6x2_mul_ckfixed-factor-clock}:Q\b;dpll4_m6x2_ck@d00ti,gate-clock};y fb<emu_per_alwon_ckfixed-factor-clock}<Q\bhclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock}+y pb>clkout2_src_mux_ck@d70ti,composite-mux-clock}+#/=y pb?clkout2_src_ckti,composite-clock}>?b@sys_clkout2@d70ti,divider-clock}@/@y pmpu_ckfixed-factor-clock}AQ\bBarm_fck@924ti,divider-clock}By $/emu_mpu_alwon_ckfixed-factor-clock}BQ\bil3_ick@a40ti,divider-clock}+/y @:bCl4_ick@a40ti,divider-clock}C/y @:bDrm_ick@c40ti,divider-clock}D/y @:gpt10_gate_fck@a00ti,composite-gate-clock}# y bFgpt10_mux_fck@a40ti,composite-mux-clock}E#y @bGgpt10_fckti,composite-clock}FGgpt11_gate_fck@a00ti,composite-gate-clock}# y bHgpt11_mux_fck@a40ti,composite-mux-clock}E#y @bIgpt11_fckti,composite-clock}HIcore_96m_fckfixed-factor-clock}JQ\bmmchs2_fck@a00ti,wait-gate-clock}y bmmchs1_fck@a00ti,wait-gate-clock}y bi2c3_fck@a00ti,wait-gate-clock}y bi2c2_fck@a00ti,wait-gate-clock}y bi2c1_fck@a00ti,wait-gate-clock}y bmcbsp5_gate_fck@a00ti,composite-gate-clock}  y b mcbsp1_gate_fck@a00ti,composite-gate-clock}  y b core_48m_fckfixed-factor-clock}5Q\bKmcspi4_fck@a00ti,wait-gate-clock}Ky bmcspi3_fck@a00ti,wait-gate-clock}Ky bmcspi2_fck@a00ti,wait-gate-clock}Ky bmcspi1_fck@a00ti,wait-gate-clock}Ky buart2_fck@a00ti,wait-gate-clock}Ky buart1_fck@a00ti,wait-gate-clock}Ky  bcore_12m_fckfixed-factor-clock}LQ\bMhdq_fck@a00ti,wait-gate-clock}My bcore_l3_ickfixed-factor-clock}CQ\bNsdrc_ick@a10ti,wait-gate-clock}Ny bgpmc_fckfixed-factor-clock}NQ\core_l4_ickfixed-factor-clock}DQ\bOmmchs2_ick@a10ti,omap3-interface-clock}Oy bmmchs1_ick@a10ti,omap3-interface-clock}Oy bhdq_ick@a10ti,omap3-interface-clock}Oy bmcspi4_ick@a10ti,omap3-interface-clock}Oy bmcspi3_ick@a10ti,omap3-interface-clock}Oy bmcspi2_ick@a10ti,omap3-interface-clock}Oy bmcspi1_ick@a10ti,omap3-interface-clock}Oy bi2c3_ick@a10ti,omap3-interface-clock}Oy bi2c2_ick@a10ti,omap3-interface-clock}Oy bi2c1_ick@a10ti,omap3-interface-clock}Oy buart2_ick@a10ti,omap3-interface-clock}Oy buart1_ick@a10ti,omap3-interface-clock}Oy  bgpt11_ick@a10ti,omap3-interface-clock}Oy  bgpt10_ick@a10ti,omap3-interface-clock}Oy  bmcbsp5_ick@a10ti,omap3-interface-clock}Oy  bmcbsp1_ick@a10ti,omap3-interface-clock}Oy  bomapctrl_ick@a10ti,omap3-interface-clock}Oy bdss_tv_fck@e00ti,gate-clock}=ybdss_96m_fck@e00ti,gate-clock}Jybdss2_alwon_fck@e00ti,gate-clock}#ybdummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock}#y bPgpt1_mux_fck@c40ti,composite-mux-clock}E#y @bQgpt1_fckti,composite-clock}PQbaes2_ick@a10ti,omap3-interface-clock}Oy bwkup_32k_fckfixed-factor-clock}EQ\bRgpio1_dbck@c00ti,gate-clock}Ry bsha12_ick@a10ti,omap3-interface-clock}Oy bwdt2_fck@c00ti,wait-gate-clock}Ry bwdt2_ick@c10ti,omap3-interface-clock}Sy bwdt1_ick@c10ti,omap3-interface-clock}Sy bgpio1_ick@c10ti,omap3-interface-clock}Sy bomap_32ksync_ick@c10ti,omap3-interface-clock}Sy bgpt12_ick@c10ti,omap3-interface-clock}Sy bgpt1_ick@c10ti,omap3-interface-clock}Sy bper_96m_fckfixed-factor-clock}.Q\bper_48m_fckfixed-factor-clock}5Q\bTuart3_fck@1000ti,wait-gate-clock}Ty bgpt2_gate_fck@1000ti,composite-gate-clock}#ybUgpt2_mux_fck@1040ti,composite-mux-clock}E#y@bVgpt2_fckti,composite-clock}UVbgpt3_gate_fck@1000ti,composite-gate-clock}#ybWgpt3_mux_fck@1040ti,composite-mux-clock}E#y@bXgpt3_fckti,composite-clock}WXgpt4_gate_fck@1000ti,composite-gate-clock}#ybYgpt4_mux_fck@1040ti,composite-mux-clock}E#y@bZgpt4_fckti,composite-clock}YZgpt5_gate_fck@1000ti,composite-gate-clock}#yb[gpt5_mux_fck@1040ti,composite-mux-clock}E#y@b\gpt5_fckti,composite-clock}[\gpt6_gate_fck@1000ti,composite-gate-clock}#yb]gpt6_mux_fck@1040ti,composite-mux-clock}E#y@b^gpt6_fckti,composite-clock}]^gpt7_gate_fck@1000ti,composite-gate-clock}#yb_gpt7_mux_fck@1040ti,composite-mux-clock}E#y@b`gpt7_fckti,composite-clock}_`gpt8_gate_fck@1000ti,composite-gate-clock}# ybagpt8_mux_fck@1040ti,composite-mux-clock}E#y@bbgpt8_fckti,composite-clock}abgpt9_gate_fck@1000ti,composite-gate-clock}# ybcgpt9_mux_fck@1040ti,composite-mux-clock}E#y@bdgpt9_fckti,composite-clock}cdper_32k_alwon_fckfixed-factor-clock}EQ\begpio6_dbck@1000ti,gate-clock}eybgpio5_dbck@1000ti,gate-clock}eybgpio4_dbck@1000ti,gate-clock}eybgpio3_dbck@1000ti,gate-clock}eybgpio2_dbck@1000ti,gate-clock}ey bwdt3_fck@1000ti,wait-gate-clock}ey bper_l4_ickfixed-factor-clock}DQ\bfgpio6_ick@1010ti,omap3-interface-clock}fybgpio5_ick@1010ti,omap3-interface-clock}fybgpio4_ick@1010ti,omap3-interface-clock}fybgpio3_ick@1010ti,omap3-interface-clock}fybgpio2_ick@1010ti,omap3-interface-clock}fy bwdt3_ick@1010ti,omap3-interface-clock}fy buart3_ick@1010ti,omap3-interface-clock}fy buart4_ick@1010ti,omap3-interface-clock}fybgpt9_ick@1010ti,omap3-interface-clock}fy bgpt8_ick@1010ti,omap3-interface-clock}fy bgpt7_ick@1010ti,omap3-interface-clock}fybgpt6_ick@1010ti,omap3-interface-clock}fybgpt5_ick@1010ti,omap3-interface-clock}fybgpt4_ick@1010ti,omap3-interface-clock}fybgpt3_ick@1010ti,omap3-interface-clock}fybgpt2_ick@1010ti,omap3-interface-clock}fybmcbsp2_ick@1010ti,omap3-interface-clock}fybmcbsp3_ick@1010ti,omap3-interface-clock}fybmcbsp4_ick@1010ti,omap3-interface-clock}fybmcbsp2_gate_fck@1000ti,composite-gate-clock} ybmcbsp3_gate_fck@1000ti,composite-gate-clock} ybmcbsp4_gate_fck@1000ti,composite-gate-clock} ybemu_src_mux_ck@1140 ti,mux-clock}#ghiy@bjemu_src_ckti,clkdm-gate-clock}jbkpclk_fck@1140ti,divider-clock}k/y@:pclkx2_fck@1140ti,divider-clock}k/y@:atclk_fck@1140ti,divider-clock}k/y@:traceclk_src_fck@1140 ti,mux-clock}#ghiy@bltraceclk_fck@1140ti,divider-clock}l /y@:secure_32k_fck fixed-clockbmgpt12_fckfixed-factor-clock}mQ\bwdt1_fckfixed-factor-clock}mQ\security_l4_ick2fixed-factor-clock}DQ\bnaes1_ick@a14ti,omap3-interface-clock}ny brng_ick@a14ti,omap3-interface-clock}ny bsha11_ick@a14ti,omap3-interface-clock}ny des1_ick@a14ti,omap3-interface-clock}ny cam_mclk@f00ti,gate-clock}oycam_ick@f10!ti,omap3-no-wait-interface-clock}Dybcsi2_96m_fck@f00ti,gate-clock}ybsecurity_l3_ickfixed-factor-clock}CQ\bppka_ick@a14ti,omap3-interface-clock}py icr_ick@a10ti,omap3-interface-clock}Oy des2_ick@a10ti,omap3-interface-clock}Oy mspro_ick@a10ti,omap3-interface-clock}Oy mailboxes_ick@a10ti,omap3-interface-clock}Oy ssi_l4_ickfixed-factor-clock}DQ\bwsr1_fck@c00ti,wait-gate-clock}#y bsr2_fck@c00ti,wait-gate-clock}#y bsr_l4_ickfixed-factor-clock}DQ\dpll2_fck@40ti,divider-clock}+/y@:bqdpll2_ck@4ti,omap3-dpll-clock}#qy$@4brdpll2_m2_ck@44ti,divider-clock}r/yD:bsiva2_ck@0ti,wait-gate-clock}sybmodem_fck@a00ti,omap3-interface-clock}#y bsad2d_ick@a10ti,omap3-interface-clock}Cy bmad2d_ick@a18ti,omap3-interface-clock}Cy bmspro_fck@a00ti,wait-gate-clock}y ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock}$y btssi_ssr_div_fck_3430es2@a40ti,composite-divider-clock}$y @$bussi_ssr_fck_3430es2ti,composite-clock}tubvssi_sst_fck_3430es2fixed-factor-clock}vQ\b hsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clock}Ny bssi_ick_3430es2@a10ti,omap3-ssi-interface-clock}wy b usim_gate_fck@c00ti,composite-gate-clock}J y bsys_d2_ckfixed-factor-clock}#Q\byomap_96m_d2_fckfixed-factor-clock}JQ\bzomap_96m_d4_fckfixed-factor-clock}JQ\b{omap_96m_d8_fckfixed-factor-clock}JQ\b|omap_96m_d10_fckfixed-factor-clock}JQ\ b}dpll5_m2_d4_ckfixed-factor-clock}xQ\b~dpll5_m2_d8_ckfixed-factor-clock}xQ\bdpll5_m2_d16_ckfixed-factor-clock}xQ\bdpll5_m2_d20_ckfixed-factor-clock}xQ\busim_mux_fck@c40ti,composite-mux-clock(}#yz{|}~y @:busim_fckti,composite-clock}usim_ick@c10ti,omap3-interface-clock}Sy  bdpll5_ck@d04ti,omap3-dpll-clock}##y  $ L 4bdpll5_m2_ck@d50ti,divider-clock}/y P:bxsgx_gate_fck@b00ti,composite-gate-clock}+y bcore_d3_ckfixed-factor-clock}+Q\bcore_d4_ckfixed-factor-clock}+Q\bcore_d6_ckfixed-factor-clock}+Q\bomap_192m_alwon_fckfixed-factor-clock}'Q\bcore_d2_ckfixed-factor-clock}+Q\bsgx_mux_fck@b40ti,composite-mux-clock }/y @bsgx_fckti,composite-clock}bsgx_ick@b10ti,wait-gate-clock}Cy bcpefuse_fck@a08ti,gate-clock}#y bts_fck@a08ti,gate-clock}Ey busbtll_fck@a08ti,wait-gate-clock}xy busbtll_ick@a18ti,omap3-interface-clock}Oy bmmchs3_ick@a10ti,omap3-interface-clock}Oy bmmchs3_fck@a00ti,wait-gate-clock}y bdss1_alwon_fck_3430es2@e00ti,dss-gate-clock}ybdss_ick_3430es2@e10ti,omap3-dss-interface-clock}Dybusbhost_120m_fck@1400ti,gate-clock}xybusbhost_48m_fck@1400ti,dss-gate-clock}5ybusbhost_ick@1410ti,omap3-dss-interface-clock}Dybclockdomainscore_l3_clkdmti,clockdomain}dpll3_clkdmti,clockdomain}dpll1_clkdmti,clockdomain}per_clkdmti,clockdomainh}emu_clkdmti,clockdomain}kdpll4_clkdmti,clockdomain}!wkup_clkdmti,clockdomain$}dss_clkdmti,clockdomain}core_l4_clkdmti,clockdomain}cam_clkdmti,clockdomain}iva2_clkdmti,clockdomain}dpll2_clkdmti,clockdomain}rd2d_clkdmti,clockdomain }dpll5_clkdmti,clockdomain}sgx_clkdmti,clockdomain}usbhost_clkdmti,clockdomain }target-module@48320000ti,sysc-omap2ti,syscyH2H2 revsysc}Rfckick+ H2counter@0ti,omap-counter32ky interrupt-controller@48200000ti,omap3-intcyH btarget-module@48056000ti,sysc-omap2ti,syscyH`H`,H`(revsyscsyss#  }Nick+ H`dma-controller@0ti,omap3430-sdmati,omap-sdmay   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compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-points-v2cpu0-supplyinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0phandlepinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftreg-namesti,sysc-maskti,sysc-sidleti,syss-maskdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsgpio-hoggpiosoutput-lowline-nameinterrupts-extendedbci3v1-supplyio-channelsio-channel-namesregulator-always-onti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cellsti,use_poweroff#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencyvcc-supplyti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,swap-xywakeup-sourcependown-gpioti,dual-voltpbias-supplyvmmc-supplyvqmmc-supplybus-widthnon-removablecap-power-off-cardinterrupt-namesref-clock-frequencystatus#iommu-cellsti,#tlb-entriesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinsbank-widthgpmc,device-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsgpmc,wr-data-mux-bus-nsgpmc,wr-access-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addresslinux,mtd-namenand-bus-widthti,nand-ecc-optgpmc,sync-clk-psmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowervdds_dsi-supplyvdda_video-supplyremote-endpointdata-linesiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendturbo-modepolling-delay-passivepolling-delaycoefficientsthermal-sensorsstartup-delay-usenable-active-highreset-gpioslabellinux,default-triggervin-supplydefault-onpower-supplyenvdd-supplyenable-gpiosmode-gpios