,8( @Uheadacoustics,omap3-ha-lcdtechnexion,omap3-tao3530ti,omap3430ti,omap34xxti,omap3 +77TI OMAP3 HEAD acoustics LCD-baseboard with TAO3530 SOMchosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000 d/displaycpus+cpu@0arm,cortex-a8mcpuy}cpupmu@54000000arm,cortex-a8-pmuyTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busyh +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-busy + pinmux@30 ti,omap3-padconfpinctrl-singley08+-Jdefault X pinmux_hsusbb2_pins`b          vpinmux_mmc1_pinsPb "$&vpinmux_mmc2_pins0b(*,.02vpinmux_wlan_gpiob^pinmux_uart3_pinsbnApvpinmux_i2c3_pinsbvpinmux_mcspi1_pins bvpinmux_mcspi3_pins bvpinmux_mcbsp3_pins b<>@Bvpinmux_twl4030_pinsbAvpinmux_sound2_pinsbnpinmux_led_blue_pinsbv pinmux_led_green_pinsbv pinmux_led_red_pinsbv pinmux_poweroff_pinsbvpinmux_powerdown_input_pinsbvfpga_boot0_pins bvfpga_boot1_pins brtvxvpinmux_touchscreen_irq_pinsb4pinmux_touchscreen_wake_pinsbv pinmux_dss_dpi_pinsbv pinmux_lte430_pinsb8vpinmux_backlight_pinsb:vscm_conf@270sysconsimple-busyp0+ p0v pbias_regulator@2b0ti,pbias-omap3ti,pbias-omapy~ pbias_mmc_omap2430pbias_mmc_omap2430w@-vclocks+mcbsp5_mux_fck@68ti,composite-mux-clock}yhvmcbsp5_fckti,composite-clock}vmcbsp1_mux_fck@4ti,composite-mux-clock}yvmcbsp1_fckti,composite-clock}vmcbsp2_mux_fck@4ti,composite-mux-clock}yvmcbsp2_fckti,composite-clock}vmcbsp3_mux_fck@68ti,composite-mux-clock}yhvmcbsp3_fckti,composite-clock}vmcbsp4_mux_fck@68ti,composite-mux-clock}yhvmcbsp4_fckti,composite-clock}vclockdomainspinmux@a00 ti,omap3-padconfpinctrl-singley \+-pinmux_twl4030_vpins bvtarget-module@480a6000ti,sysc-omap2ti,syscyH `DH `HH `Lrevsyscsyss }ick+ H `  disabledaes1@0 ti,omap3-aesyP  txrxtarget-module@480c5000ti,sysc-omap2ti,syscyH PDH PHH PLrevsyscsyss }ick+ H P  disabledaes2@0 ti,omap3-aesyPABtxrxprm@48306000 ti,omap3-prmyH0`@ clocks+virt_16_8m_ck fixed-clock&Yv#osc_sys_ck@d40 ti,mux-clock} !"#y @v$sys_ck@1270ti,divider-clock}$6ypAv)sys_clkout1@d70ti,gate-clock}$y pdpll3_x2_ckfixed-factor-clock}%Xcdpll3_m2x2_ckfixed-factor-clock}&Xcv(dpll4_x2_ckfixed-factor-clock}'Xccorex2_fckfixed-factor-clock}(Xcv*wkup_l4_ickfixed-factor-clock})XcvYcorex2_d3_fckfixed-factor-clock}*Xcvcorex2_d5_fckfixed-factor-clock}*Xcvclockdomainscm@48004000 ti,omap3-cmyH@@clocks+dummy_apb_pclk fixed-clock&omap_32k_fck fixed-clock&vKvirt_12m_ck fixed-clock&vvirt_13m_ck fixed-clock&]@vvirt_19200000_ck fixed-clock&$v virt_26000000_ck fixed-clock&v!virt_38_4m_ck fixed-clock&Iv"dpll4_ck@d00ti,omap3-dpll-per-clock}))y D 0v'dpll4_m2_ck@d48ti,divider-clock}'6?y HAv+dpll4_m2x2_mul_ckfixed-factor-clock}+Xcv,dpll4_m2x2_ck@d00ti,gate-clock},y mv-omap_96m_alwon_fckfixed-factor-clock}-Xcv4dpll3_ck@d00ti,omap3-dpll-core-clock}))y @ 0v%dpll3_m3_ck@1140ti,divider-clock}%6y@Av.dpll3_m3x2_mul_ckfixed-factor-clock}.Xcv/dpll3_m3x2_ck@d00ti,gate-clock}/ y mv0emu_core_alwon_ckfixed-factor-clock}0Xcvmsys_altclk fixed-clock&v9mcbsp_clks fixed-clock&vdpll3_m2_ck@d40ti,divider-clock}%6y @Av&core_ckfixed-factor-clock}&Xcv1dpll1_fck@940ti,divider-clock}16y @Av2dpll1_ck@904ti,omap3-dpll-clock})2y  $ @ 4vdpll1_x2_ckfixed-factor-clock}Xcv3dpll1_x2m2_ck@944ti,divider-clock}36y DAvGcm_96m_fckfixed-factor-clock}4Xcv5omap_96m_fck@d40 ti,mux-clock}5)y @vPdpll4_m3_ck@e40ti,divider-clock}'6 y@Av6dpll4_m3x2_mul_ckfixed-factor-clock}6Xcv7dpll4_m3x2_ck@d00ti,gate-clock}7y mv8omap_54m_fck@d40 ti,mux-clock}89y @vCcm_96m_d2_fckfixed-factor-clock}5Xcv:omap_48m_fck@d40 ti,mux-clock}:9y @v;omap_12m_fckfixed-factor-clock};XcvRdpll4_m4_ck@e40ti,divider-clock}'6y@Av<dpll4_m4x2_mul_ckti,fixed-factor-clock}<v=dpll4_m4x2_ck@d00ti,gate-clock}=y mvdpll4_m5_ck@f40ti,divider-clock}'6?y@Av>dpll4_m5x2_mul_ckti,fixed-factor-clock}>v?dpll4_m5x2_ck@d00ti,gate-clock}?y mvudpll4_m6_ck@1140ti,divider-clock}'6?y@Av@dpll4_m6x2_mul_ckfixed-factor-clock}@XcvAdpll4_m6x2_ck@d00ti,gate-clock}Ay mvBemu_per_alwon_ckfixed-factor-clock}BXcvnclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock}1y pvDclkout2_src_mux_ck@d70ti,composite-mux-clock}1)5Cy pvEclkout2_src_ckti,composite-clock}DEvFsys_clkout2@d70ti,divider-clock}F6@y pmpu_ckfixed-factor-clock}GXcvHarm_fck@924ti,divider-clock}Hy $6emu_mpu_alwon_ckfixed-factor-clock}HXcvol3_ick@a40ti,divider-clock}16y @AvIl4_ick@a40ti,divider-clock}I6y @AvJrm_ick@c40ti,divider-clock}J6y @Agpt10_gate_fck@a00ti,composite-gate-clock}) y vLgpt10_mux_fck@a40ti,composite-mux-clock}K)y @vMgpt10_fckti,composite-clock}LMgpt11_gate_fck@a00ti,composite-gate-clock}) y vNgpt11_mux_fck@a40ti,composite-mux-clock}K)y @vOgpt11_fckti,composite-clock}NOcore_96m_fckfixed-factor-clock}PXcvmmchs2_fck@a00ti,wait-gate-clock}y vmmchs1_fck@a00ti,wait-gate-clock}y vi2c3_fck@a00ti,wait-gate-clock}y vi2c2_fck@a00ti,wait-gate-clock}y vi2c1_fck@a00ti,wait-gate-clock}y vmcbsp5_gate_fck@a00ti,composite-gate-clock} y vmcbsp1_gate_fck@a00ti,composite-gate-clock} y vcore_48m_fckfixed-factor-clock};XcvQmcspi4_fck@a00ti,wait-gate-clock}Qy vmcspi3_fck@a00ti,wait-gate-clock}Qy vmcspi2_fck@a00ti,wait-gate-clock}Qy vmcspi1_fck@a00ti,wait-gate-clock}Qy vuart2_fck@a00ti,wait-gate-clock}Qy vuart1_fck@a00ti,wait-gate-clock}Qy  vcore_12m_fckfixed-factor-clock}RXcvShdq_fck@a00ti,wait-gate-clock}Sy vcore_l3_ickfixed-factor-clock}IXcvTsdrc_ick@a10ti,wait-gate-clock}Ty vgpmc_fckfixed-factor-clock}TXccore_l4_ickfixed-factor-clock}JXcvUmmchs2_ick@a10ti,omap3-interface-clock}Uy vmmchs1_ick@a10ti,omap3-interface-clock}Uy vhdq_ick@a10ti,omap3-interface-clock}Uy vmcspi4_ick@a10ti,omap3-interface-clock}Uy vmcspi3_ick@a10ti,omap3-interface-clock}Uy vmcspi2_ick@a10ti,omap3-interface-clock}Uy vmcspi1_ick@a10ti,omap3-interface-clock}Uy vi2c3_ick@a10ti,omap3-interface-clock}Uy vi2c2_ick@a10ti,omap3-interface-clock}Uy vi2c1_ick@a10ti,omap3-interface-clock}Uy vuart2_ick@a10ti,omap3-interface-clock}Uy vuart1_ick@a10ti,omap3-interface-clock}Uy  vgpt11_ick@a10ti,omap3-interface-clock}Uy  vgpt10_ick@a10ti,omap3-interface-clock}Uy  vmcbsp5_ick@a10ti,omap3-interface-clock}Uy  vmcbsp1_ick@a10ti,omap3-interface-clock}Uy  vomapctrl_ick@a10ti,omap3-interface-clock}Uy vdss_tv_fck@e00ti,gate-clock}Cyvdss_96m_fck@e00ti,gate-clock}Pyvdss2_alwon_fck@e00ti,gate-clock})yvdummy_ck fixed-clock&gpt1_gate_fck@c00ti,composite-gate-clock})y vVgpt1_mux_fck@c40ti,composite-mux-clock}K)y @vWgpt1_fckti,composite-clock}VWvaes2_ick@a10ti,omap3-interface-clock}Uy vwkup_32k_fckfixed-factor-clock}KXcvXgpio1_dbck@c00ti,gate-clock}Xy vsha12_ick@a10ti,omap3-interface-clock}Uy vwdt2_fck@c00ti,wait-gate-clock}Xy vwdt2_ick@c10ti,omap3-interface-clock}Yy vwdt1_ick@c10ti,omap3-interface-clock}Yy vgpio1_ick@c10ti,omap3-interface-clock}Yy vomap_32ksync_ick@c10ti,omap3-interface-clock}Yy vgpt12_ick@c10ti,omap3-interface-clock}Yy vgpt1_ick@c10ti,omap3-interface-clock}Yy vper_96m_fckfixed-factor-clock}4Xcvper_48m_fckfixed-factor-clock};XcvZuart3_fck@1000ti,wait-gate-clock}Zy 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vgpt7_ick@1010ti,omap3-interface-clock}lyvgpt6_ick@1010ti,omap3-interface-clock}lyvgpt5_ick@1010ti,omap3-interface-clock}lyvgpt4_ick@1010ti,omap3-interface-clock}lyvgpt3_ick@1010ti,omap3-interface-clock}lyvgpt2_ick@1010ti,omap3-interface-clock}lyvmcbsp2_ick@1010ti,omap3-interface-clock}lyvmcbsp3_ick@1010ti,omap3-interface-clock}lyvmcbsp4_ick@1010ti,omap3-interface-clock}lyvmcbsp2_gate_fck@1000ti,composite-gate-clock}yvmcbsp3_gate_fck@1000ti,composite-gate-clock}yvmcbsp4_gate_fck@1000ti,composite-gate-clock}yvemu_src_mux_ck@1140 ti,mux-clock})mnoy@vpemu_src_ckti,clkdm-gate-clock}pvqpclk_fck@1140ti,divider-clock}q6y@Apclkx2_fck@1140ti,divider-clock}q6y@Aatclk_fck@1140ti,divider-clock}q6y@Atraceclk_src_fck@1140 ti,mux-clock})mnoy@vrtraceclk_fck@1140ti,divider-clock}r 6y@Asecure_32k_fck fixed-clock&vsgpt12_fckfixed-factor-clock}sXcvwdt1_fckfixed-factor-clock}sXcsecurity_l4_ick2fixed-factor-clock}JXcvtaes1_ick@a14ti,omap3-interface-clock}ty vrng_ick@a14ti,omap3-interface-clock}ty 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@$v{ssi_ssr_fck_3430es2ti,composite-clock}z{v|ssi_sst_fck_3430es2fixed-factor-clock}|Xcv hsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clock}Ty vssi_ick_3430es2@a10ti,omap3-ssi-interface-clock}}y vusim_gate_fck@c00ti,composite-gate-clock}P y vsys_d2_ckfixed-factor-clock})Xcvomap_96m_d2_fckfixed-factor-clock}PXcvomap_96m_d4_fckfixed-factor-clock}PXcvomap_96m_d8_fckfixed-factor-clock}PXcvomap_96m_d10_fckfixed-factor-clock}PXc vdpll5_m2_d4_ckfixed-factor-clock}~Xcvdpll5_m2_d8_ckfixed-factor-clock}~Xcvdpll5_m2_d16_ckfixed-factor-clock}~Xcvdpll5_m2_d20_ckfixed-factor-clock}~Xcvusim_mux_fck@c40ti,composite-mux-clock(})y @Avusim_fckti,composite-clock}usim_ick@c10ti,omap3-interface-clock}Yy  vdpll5_ck@d04ti,omap3-dpll-clock}))y  $ L 4vdpll5_m2_ck@d50ti,divider-clock}6y PAv~sgx_gate_fck@b00ti,composite-gate-clock}1y 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$sysc}fck+ H smartreflex@480c9000ti,omap3-smartreflex-mpu-ivaytarget-module@50000000ti,sysc-omap2ti,syscyPrev}fckick+ P@opp-tableoperating-points-v2-ti-cpu~ vopp1-125000000sY@ opp2-250000000沀 g8g8g8opp3-500000000e OOOopp4-550000000 U txtxtxopp5-600000000#F pppopp6-720000000*T pppthermal-zonescpu_thermal4BN Omemory@80000000mmemoryyhsusb2_power_regregulator-fixed hsusb2_vbus2Z2Z _dpvhsusb2_phyusb-nop-xceiv u vsoundti,omap-twl4030 omap3beagleregulator-mmc2-sdio-poweronregulator-fixedregulator-mmc2-sdio-poweron00 _d'vgpio_poweroffJdefaultXgpio-poweroff display panel-dpiTlcdJdefaultX  portendpointv panel-timing&P (V     %backlightgpio-backlightJdefaultX   5 compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-points-v2cpu0-supplyinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinsphandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftreg-namesti,sysc-maskti,sysc-sidleti,syss-maskstatusdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyio-channelsio-channel-namesregulator-always-onti,use-ledsti,pullupsti,pulldownsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencyspi-cphati,dual-voltpbias-supplyvmmc-supplyvqmmc-supplycd-gpiosbus-widthnon-removablecap-power-off-card#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,wr-access-nslabelmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerremote-endpointdata-linesiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendturbo-modepolling-delay-passivepolling-delaycoefficientsthermal-sensorsgpiostartup-delay-usreset-gpiosvcc-supplyti,modelti,mcbspenable-gpioshactivevactivehfront-porchhback-porchhsync-lenvback-porchvfront-porchvsync-lenhsync-activevsync-activede-activepixelclk-activedefault-on