8( t"ti,omap3-ldpti,omap3430ti,omap3 +!7TI OMAP3430 LDP (Zoom1 Labrador)chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000 d/displaycpus+cpu@0arm,cortex-a8mcpuy}cpupmu@54000000arm,cortex-a8-pmuyTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busyh +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-busy + pinmux@30 ti,omap3-padconfpinctrl-singley08+-Jpinmux_twl4030_pinsRAJpinmux_gpio_key_pinsHRJpinmux_musb_pins`Rrz|~vxtJpinmux_mmc1_pins0RJscm_conf@270sysconsimple-busyp0+ p0Jpbias_regulator@2b0ti,pbias-omap3ti,pbias-omapyfpbias_mmc_omap2430mpbias_mmc_omap2430|w@-Jclocks+mcbsp5_mux_fck@68ti,composite-mux-clock}yhJ mcbsp5_fckti,composite-clock} Jmcbsp1_mux_fck@4ti,composite-mux-clock}yJ mcbsp1_fckti,composite-clock} Jmcbsp2_mux_fck@4ti,composite-mux-clock} yJmcbsp2_fckti,composite-clock} Jmcbsp3_mux_fck@68ti,composite-mux-clock} yhJmcbsp3_fckti,composite-clock}Jmcbsp4_mux_fck@68ti,composite-mux-clock} yhJmcbsp4_fckti,composite-clock}Jclockdomainspinmux@a00 ti,omap3-padconfpinctrl-singley \+-pinmux_twl4030_vpins RJtarget-module@480a6000ti,sysc-omap2ti,syscyH `DH `HH `Lrevsyscsyss }ick+ H ` aes1@0 ti,omap3-aesyP  txrxtarget-module@480c5000ti,sysc-omap2ti,syscyH PDH PHH PLrevsyscsyss }ick+ H P aes2@0 ti,omap3-aesyPABtxrxprm@48306000 ti,omap3-prmyH0`@ clocks+virt_16_8m_ck fixed-clockYJosc_sys_ck@d40 ti,mux-clock}y @Jsys_ck@1270ti,divider-clock}yp"J!sys_clkout1@d70ti,gate-clock}y pdpll3_x2_ckfixed-factor-clock}9Ddpll3_m2x2_ckfixed-factor-clock}9DJ dpll4_x2_ckfixed-factor-clock}9Dcorex2_fckfixed-factor-clock} 9DJ"wkup_l4_ickfixed-factor-clock}!9DJQcorex2_d3_fckfixed-factor-clock}"9DJcorex2_d5_fckfixed-factor-clock}"9DJclockdomainscm@48004000 ti,omap3-cmyH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clockJCvirt_12m_ck fixed-clockJvirt_13m_ck fixed-clock]@Jvirt_19200000_ck fixed-clock$Jvirt_26000000_ck fixed-clockJvirt_38_4m_ck fixed-clockIJdpll4_ck@d00ti,omap3-dpll-per-clock}!!y D 0Jdpll4_m2_ck@d48ti,divider-clock}?y H"J#dpll4_m2x2_mul_ckfixed-factor-clock}#9DJ$dpll4_m2x2_ck@d00ti,gate-clock}$y NJ%omap_96m_alwon_fckfixed-factor-clock}%9DJ,dpll3_ck@d00ti,omap3-dpll-core-clock}!!y @ 0Jdpll3_m3_ck@1140ti,divider-clock}y@"J&dpll3_m3x2_mul_ckfixed-factor-clock}&9DJ'dpll3_m3x2_ck@d00ti,gate-clock}' y NJ(emu_core_alwon_ckfixed-factor-clock}(9DJesys_altclk fixed-clockJ1mcbsp_clks fixed-clockJdpll3_m2_ck@d40ti,divider-clock}y @"Jcore_ckfixed-factor-clock}9DJ)dpll1_fck@940ti,divider-clock})y @"J*dpll1_ck@904ti,omap3-dpll-clock}!*y  $ @ 4Jdpll1_x2_ckfixed-factor-clock}9DJ+dpll1_x2m2_ck@944ti,divider-clock}+y D"J?cm_96m_fckfixed-factor-clock},9DJ-omap_96m_fck@d40 ti,mux-clock}-!y @JHdpll4_m3_ck@e40ti,divider-clock} y@"J.dpll4_m3x2_mul_ckfixed-factor-clock}.9DJ/dpll4_m3x2_ck@d00ti,gate-clock}/y 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smartreflex@480c9000ti,omap3-smartreflex-mpu-ivaytarget-module@50000000ti,sysc-omap2ti,syscyPrev}fckick+ P@opp-tableoperating-points-v2-ti-cpufJopp1-125000000 'sY@ . <opp2-250000000 '沀 .g8g8g8 < Mopp3-500000000 'e .OOO <opp4-550000000 ' U .txtxtx <opp5-600000000 '#F .ppp <opp6-720000000 '*T .ppp < Ythermal-zonescpu_thermal d z N  regulator-vddvarioregulator-fixed mvddvarioJregulator-vdd33aregulator-fixedmvdd33aJmemory@80000000mmemoryygpio_keys gpio-keysWdefaultekey_enterenter    key_f1f1   ; key_f2f2   < key_f3f3   = key_f4f4   > key_leftleft   i key_rightright   j key_upup   g key_downdown   l backlightgpio-backlight   regulator-lcd-3v3regulator-fixedmlcd_3v3|2Z2Z pJdisplaysharp,ls037v7dw01lcd      portendpoint J compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-points-v2cpu0-supplyinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskphandlepinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftreg-namesti,sysc-maskti,sysc-sidleti,syss-maskdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0ti,use_poweroffbci3v1-supplyio-channelsio-channel-namesregulator-always-onusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencyvcc-supplyti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,swap-xywakeup-sourcependown-gpioti,dual-voltpbias-supplyvmmc-supplybus-widthstatus#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureremote-wakeup-connectedgpmc,num-csgpmc,num-waitpinsbank-widthgpmc,device-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsgpmc,wr-data-mux-bus-nsgpmc,wr-access-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addresslinux,mtd-namenand-bus-widthti,nand-ecc-optgpmc,sync-clk-pslabelmultipointnum-epsram-bitsinterface-typeusb-phypowerremote-endpointdata-linesiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendturbo-modepolling-delay-passivepolling-delaycoefficientsthermal-sensorsgpioslinux,codedefault-onstartup-delay-uspower-supplyenvdd-supplyenable-gpiosreset-gpiosmode-gpios