H8( PQgumstix,omap3-overo-tobiduogumstix,omap3-overoti,omap3630ti,omap36xxti,omap3 +07OMAP36xx/AM37xx/DM37xx Gumstix Overo on TobiDuochosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000d/ocp@68000000/serial@49042000cpus+cpu@0arm,cortex-a8lcpux|cpupmu@54000000arm,cortex-a8-pmuxTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busxh +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-busx + pinmux@30 ti,omap3-padconfpinctrl-singlex08+ +HdefaultV`pinmux_uart2_pins h<>@B`pinmux_i2c1_pinsh`pinmux_mmc1_pins0h`pinmux_mmc2_pins0h(*,.02`pinmux_w3cbw003c_pinshl`pinmux_hsusb2_pins@h      `pinmux_twl4030_pinshA`pinmux_i2c3_pinsh`pinmux_uart3_pinshnp`scm_conf@270sysconsimple-busxp0+ p0`pbias_regulator@2b0ti,pbias-omap3ti,pbias-omapx|pbias_mmc_omap2430pbias_mmc_omap2430w@-`clocks+mcbsp5_mux_fck@68ti,composite-mux-clock|xh` mcbsp5_fckti,composite-clock| `mcbsp1_mux_fck@4ti,composite-mux-clock|x` mcbsp1_fckti,composite-clock| `mcbsp2_mux_fck@4ti,composite-mux-clock| x`mcbsp2_fckti,composite-clock|`mcbsp3_mux_fck@68ti,composite-mux-clock| xh`mcbsp3_fckti,composite-clock|`mcbsp4_mux_fck@68ti,composite-mux-clock| xh`mcbsp4_fckti,composite-clock|`clockdomainspinmux@a00 ti,omap3-padconfpinctrl-singlex \+ +pinmux_twl4030_vpins h`target-module@480a6000ti,sysc-omap2ti,syscxH `DH `HH `Lrevsyscsyss |ick+ H ` aes1@0 ti,omap3-aesxP  txrxtarget-module@480c5000ti,sysc-omap2ti,syscxH PDH PHH PLrevsyscsyss |ick+ H P aes2@0 ti,omap3-aesxPABtxrxprm@48306000 ti,omap3-prmxH0`@ clocks+virt_16_8m_ck fixed-clockY`osc_sys_ck@d40 ti,mux-clock|x @`sys_ck@1270ti,divider-clock|-xp8`"sys_clkout1@d70ti,gate-clock|x pdpll3_x2_ckfixed-factor-clock|OZdpll3_m2x2_ckfixed-factor-clock|OZ`!dpll4_x2_ckfixed-factor-clock| OZcorex2_fckfixed-factor-clock|!OZ`#wkup_l4_ickfixed-factor-clock|"OZ`Rcorex2_d3_fckfixed-factor-clock|#OZ`corex2_d5_fckfixed-factor-clock|#OZ`clockdomainscm@48004000 ti,omap3-cmxH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clock`Dvirt_12m_ck fixed-clock`virt_13m_ck fixed-clock]@`virt_19200000_ck fixed-clock$`virt_26000000_ck fixed-clock`virt_38_4m_ck fixed-clockI`dpll4_ck@d00ti,omap3-dpll-per-j-type-clock|""x D 0` dpll4_m2_ck@d48ti,divider-clock| -?x H8`$dpll4_m2x2_mul_ckfixed-factor-clock|$OZ`%dpll4_m2x2_ck@d00ti,hsdiv-gate-clock|%x d`&omap_96m_alwon_fckfixed-factor-clock|&OZ`-dpll3_ck@d00ti,omap3-dpll-core-clock|""x @ 0`dpll3_m3_ck@1140ti,divider-clock|-x@8`'dpll3_m3x2_mul_ckfixed-factor-clock|'OZ`(dpll3_m3x2_ck@d00ti,hsdiv-gate-clock|( x d`)emu_core_alwon_ckfixed-factor-clock|)OZ`fsys_altclk fixed-clock`2mcbsp_clks fixed-clock`dpll3_m2_ck@d40ti,divider-clock|-x @8`core_ckfixed-factor-clock|OZ`*dpll1_fck@940ti,divider-clock|*-x @8`+dpll1_ck@904ti,omap3-dpll-clock|"+x  $ @ 4`dpll1_x2_ckfixed-factor-clock|OZ`,dpll1_x2m2_ck@944ti,divider-clock|,-x D8`@cm_96m_fckfixed-factor-clock|-OZ`.omap_96m_fck@d40 ti,mux-clock|."x @`Idpll4_m3_ck@e40ti,divider-clock| - x@8`/dpll4_m3x2_mul_ckfixed-factor-clock|/OZ`0dpll4_m3x2_ck@d00ti,hsdiv-gate-clock|0x d`1omap_54m_fck@d40 ti,mux-clock|12x @`<cm_96m_d2_fckfixed-factor-clock|.OZ`3omap_48m_fck@d40 ti,mux-clock|32x @`4omap_12m_fckfixed-factor-clock|4OZ`Kdpll4_m4_ck@e40ti,divider-clock| -x@8`5dpll4_m4x2_mul_ckti,fixed-factor-clock|5z`6dpll4_m4x2_ck@d00ti,gate-clock|6x d`dpll4_m5_ck@f40ti,divider-clock| -?x@8`7dpll4_m5x2_mul_ckti,fixed-factor-clock|7z`8dpll4_m5x2_ck@d00ti,hsdiv-gate-clock|8x d`ndpll4_m6_ck@1140ti,divider-clock| -?x@8`9dpll4_m6x2_mul_ckfixed-factor-clock|9OZ`:dpll4_m6x2_ck@d00ti,hsdiv-gate-clock|:x d`;emu_per_alwon_ckfixed-factor-clock|;OZ`gclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock|*x p`=clkout2_src_mux_ck@d70ti,composite-mux-clock|*".<x p`>clkout2_src_ckti,composite-clock|=>`?sys_clkout2@d70ti,divider-clock|?-@x pmpu_ckfixed-factor-clock|@OZ`Aarm_fck@924ti,divider-clock|Ax $-emu_mpu_alwon_ckfixed-factor-clock|AOZ`hl3_ick@a40ti,divider-clock|*-x @8`Bl4_ick@a40ti,divider-clock|B-x @8`Crm_ick@c40ti,divider-clock|C-x @8gpt10_gate_fck@a00ti,composite-gate-clock|" x `Egpt10_mux_fck@a40ti,composite-mux-clock|D"x @`Fgpt10_fckti,composite-clock|EFgpt11_gate_fck@a00ti,composite-gate-clock|" x `Ggpt11_mux_fck@a40ti,composite-mux-clock|D"x @`Hgpt11_fckti,composite-clock|GHcore_96m_fckfixed-factor-clock|IOZ`mmchs2_fck@a00ti,wait-gate-clock|x `mmchs1_fck@a00ti,wait-gate-clock|x `i2c3_fck@a00ti,wait-gate-clock|x `i2c2_fck@a00ti,wait-gate-clock|x `i2c1_fck@a00ti,wait-gate-clock|x `mcbsp5_gate_fck@a00ti,composite-gate-clock| x ` mcbsp1_gate_fck@a00ti,composite-gate-clock| x ` core_48m_fckfixed-factor-clock|4OZ`Jmcspi4_fck@a00ti,wait-gate-clock|Jx `mcspi3_fck@a00ti,wait-gate-clock|Jx `mcspi2_fck@a00ti,wait-gate-clock|Jx `mcspi1_fck@a00ti,wait-gate-clock|Jx `uart2_fck@a00ti,wait-gate-clock|Jx `uart1_fck@a00ti,wait-gate-clock|Jx  `core_12m_fckfixed-factor-clock|KOZ`Lhdq_fck@a00ti,wait-gate-clock|Lx `core_l3_ickfixed-factor-clock|BOZ`Msdrc_ick@a10ti,wait-gate-clock|Mx `gpmc_fckfixed-factor-clock|MOZcore_l4_ickfixed-factor-clock|COZ`Nmmchs2_ick@a10ti,omap3-interface-clock|Nx `mmchs1_ick@a10ti,omap3-interface-clock|Nx `hdq_ick@a10ti,omap3-interface-clock|Nx `mcspi4_ick@a10ti,omap3-interface-clock|Nx `mcspi3_ick@a10ti,omap3-interface-clock|Nx `mcspi2_ick@a10ti,omap3-interface-clock|Nx `mcspi1_ick@a10ti,omap3-interface-clock|Nx `i2c3_ick@a10ti,omap3-interface-clock|Nx `i2c2_ick@a10ti,omap3-interface-clock|Nx `i2c1_ick@a10ti,omap3-interface-clock|Nx `uart2_ick@a10ti,omap3-interface-clock|Nx `uart1_ick@a10ti,omap3-interface-clock|Nx  `gpt11_ick@a10ti,omap3-interface-clock|Nx  `gpt10_ick@a10ti,omap3-interface-clock|Nx  `mcbsp5_ick@a10ti,omap3-interface-clock|Nx  `mcbsp1_ick@a10ti,omap3-interface-clock|Nx  `omapctrl_ick@a10ti,omap3-interface-clock|Nx `dss_tv_fck@e00ti,gate-clock|<x`dss_96m_fck@e00ti,gate-clock|Ix`dss2_alwon_fck@e00ti,gate-clock|"x`dummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock|"x `Ogpt1_mux_fck@c40ti,composite-mux-clock|D"x @`Pgpt1_fckti,composite-clock|OP`aes2_ick@a10ti,omap3-interface-clock|Nx `wkup_32k_fckfixed-factor-clock|DOZ`Qgpio1_dbck@c00ti,gate-clock|Qx `sha12_ick@a10ti,omap3-interface-clock|Nx `wdt2_fck@c00ti,wait-gate-clock|Qx `wdt2_ick@c10ti,omap3-interface-clock|Rx `wdt1_ick@c10ti,omap3-interface-clock|Rx `gpio1_ick@c10ti,omap3-interface-clock|Rx `omap_32ksync_ick@c10ti,omap3-interface-clock|Rx `gpt12_ick@c10ti,omap3-interface-clock|Rx `gpt1_ick@c10ti,omap3-interface-clock|Rx `per_96m_fckfixed-factor-clock|-OZ` per_48m_fckfixed-factor-clock|4OZ`Suart3_fck@1000ti,wait-gate-clock|Sx `gpt2_gate_fck@1000ti,composite-gate-clock|"x`Tgpt2_mux_fck@1040ti,composite-mux-clock|D"x@`Ugpt2_fckti,composite-clock|TU`gpt3_gate_fck@1000ti,composite-gate-clock|"x`Vgpt3_mux_fck@1040ti,composite-mux-clock|D"x@`Wgpt3_fckti,composite-clock|VWgpt4_gate_fck@1000ti,composite-gate-clock|"x`Xgpt4_mux_fck@1040ti,composite-mux-clock|D"x@`Ygpt4_fckti,composite-clock|XYgpt5_gate_fck@1000ti,composite-gate-clock|"x`Zgpt5_mux_fck@1040ti,composite-mux-clock|D"x@`[gpt5_fckti,composite-clock|Z[gpt6_gate_fck@1000ti,composite-gate-clock|"x`\gpt6_mux_fck@1040ti,composite-mux-clock|D"x@`]gpt6_fckti,composite-clock|\]gpt7_gate_fck@1000ti,composite-gate-clock|"x`^gpt7_mux_fck@1040ti,composite-mux-clock|D"x@`_gpt7_fckti,composite-clock|^_gpt8_gate_fck@1000ti,composite-gate-clock|" x``gpt8_mux_fck@1040ti,composite-mux-clock|D"x@`agpt8_fckti,composite-clock|`agpt9_gate_fck@1000ti,composite-gate-clock|" x`bgpt9_mux_fck@1040ti,composite-mux-clock|D"x@`cgpt9_fckti,composite-clock|bcper_32k_alwon_fckfixed-factor-clock|DOZ`dgpio6_dbck@1000ti,gate-clock|dx`gpio5_dbck@1000ti,gate-clock|dx`gpio4_dbck@1000ti,gate-clock|dx`gpio3_dbck@1000ti,gate-clock|dx`gpio2_dbck@1000ti,gate-clock|dx `wdt3_fck@1000ti,wait-gate-clock|dx `per_l4_ickfixed-factor-clock|COZ`egpio6_ick@1010ti,omap3-interface-clock|ex`gpio5_ick@1010ti,omap3-interface-clock|ex`gpio4_ick@1010ti,omap3-interface-clock|ex`gpio3_ick@1010ti,omap3-interface-clock|ex`gpio2_ick@1010ti,omap3-interface-clock|ex `wdt3_ick@1010ti,omap3-interface-clock|ex `uart3_ick@1010ti,omap3-interface-clock|ex `uart4_ick@1010ti,omap3-interface-clock|ex`gpt9_ick@1010ti,omap3-interface-clock|ex `gpt8_ick@1010ti,omap3-interface-clock|ex `gpt7_ick@1010ti,omap3-interface-clock|ex`gpt6_ick@1010ti,omap3-interface-clock|ex`gpt5_ick@1010ti,omap3-interface-clock|ex`gpt4_ick@1010ti,omap3-interface-clock|ex`gpt3_ick@1010ti,omap3-interface-clock|ex`gpt2_ick@1010ti,omap3-interface-clock|ex`mcbsp2_ick@1010ti,omap3-interface-clock|ex`mcbsp3_ick@1010ti,omap3-interface-clock|ex`mcbsp4_ick@1010ti,omap3-interface-clock|ex`mcbsp2_gate_fck@1000ti,composite-gate-clock|x`mcbsp3_gate_fck@1000ti,composite-gate-clock|x`mcbsp4_gate_fck@1000ti,composite-gate-clock|x`emu_src_mux_ck@1140 ti,mux-clock|"fghx@`iemu_src_ckti,clkdm-gate-clock|i`jpclk_fck@1140ti,divider-clock|j-x@8pclkx2_fck@1140ti,divider-clock|j-x@8atclk_fck@1140ti,divider-clock|j-x@8traceclk_src_fck@1140 ti,mux-clock|"fghx@`ktraceclk_fck@1140ti,divider-clock|k -x@8secure_32k_fck fixed-clock`lgpt12_fckfixed-factor-clock|lOZ`wdt1_fckfixed-factor-clock|lOZsecurity_l4_ick2fixed-factor-clock|COZ`maes1_ick@a14ti,omap3-interface-clock|mx `rng_ick@a14ti,omap3-interface-clock|mx `sha11_ick@a14ti,omap3-interface-clock|mx des1_ick@a14ti,omap3-interface-clock|mx cam_mclk@f00ti,gate-clock|nxcam_ick@f10!ti,omap3-no-wait-interface-clock|Cx`csi2_96m_fck@f00ti,gate-clock|x`security_l3_ickfixed-factor-clock|BOZ`opka_ick@a14ti,omap3-interface-clock|ox icr_ick@a10ti,omap3-interface-clock|Nx des2_ick@a10ti,omap3-interface-clock|Nx mspro_ick@a10ti,omap3-interface-clock|Nx mailboxes_ick@a10ti,omap3-interface-clock|Nx ssi_l4_ickfixed-factor-clock|COZ`vsr1_fck@c00ti,wait-gate-clock|"x `sr2_fck@c00ti,wait-gate-clock|"x `sr_l4_ickfixed-factor-clock|COZdpll2_fck@40ti,divider-clock|*-x@8`pdpll2_ck@4ti,omap3-dpll-clock|"px$@4`qdpll2_m2_ck@44ti,divider-clock|q-xD8`riva2_ck@0ti,wait-gate-clock|rx`modem_fck@a00ti,omap3-interface-clock|"x `sad2d_ick@a10ti,omap3-interface-clock|Bx `mad2d_ick@a18ti,omap3-interface-clock|Bx `mspro_fck@a00ti,wait-gate-clock|x ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock|#x `sssi_ssr_div_fck_3430es2@a40ti,composite-divider-clock|#x @$`tssi_ssr_fck_3430es2ti,composite-clock|st`ussi_sst_fck_3430es2fixed-factor-clock|uOZ` hsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clock|Mx `ssi_ick_3430es2@a10ti,omap3-ssi-interface-clock|vx ` usim_gate_fck@c00ti,composite-gate-clock|I x `sys_d2_ckfixed-factor-clock|"OZ`xomap_96m_d2_fckfixed-factor-clock|IOZ`yomap_96m_d4_fckfixed-factor-clock|IOZ`zomap_96m_d8_fckfixed-factor-clock|IOZ`{omap_96m_d10_fckfixed-factor-clock|IOZ `|dpll5_m2_d4_ckfixed-factor-clock|wOZ`}dpll5_m2_d8_ckfixed-factor-clock|wOZ`~dpll5_m2_d16_ckfixed-factor-clock|wOZ`dpll5_m2_d20_ckfixed-factor-clock|wOZ`usim_mux_fck@c40ti,composite-mux-clock(|"xyz{|}~x @8`usim_fckti,composite-clock|usim_ick@c10ti,omap3-interface-clock|Rx  `dpll5_ck@d04ti,omap3-dpll-clock|""x  $ L 4`dpll5_m2_ck@d50ti,divider-clock|-x P8`wsgx_gate_fck@b00ti,composite-gate-clock|*x `core_d3_ckfixed-factor-clock|*OZ`core_d4_ckfixed-factor-clock|*OZ`core_d6_ckfixed-factor-clock|*OZ`omap_192m_alwon_fckfixed-factor-clock|&OZ`core_d2_ckfixed-factor-clock|*OZ`sgx_mux_fck@b40ti,composite-mux-clock |.x @`sgx_fckti,composite-clock|`sgx_ick@b10ti,wait-gate-clock|Bx `cpefuse_fck@a08ti,gate-clock|"x `ts_fck@a08ti,gate-clock|Dx `usbtll_fck@a08ti,wait-gate-clock|wx `usbtll_ick@a18ti,omap3-interface-clock|Nx `mmchs3_ick@a10ti,omap3-interface-clock|Nx `mmchs3_fck@a00ti,wait-gate-clock|x `dss1_alwon_fck_3430es2@e00ti,dss-gate-clock|x`dss_ick_3430es2@e10ti,omap3-dss-interface-clock|Cx`usbhost_120m_fck@1400ti,gate-clock|wx`usbhost_48m_fck@1400ti,dss-gate-clock|4x`usbhost_ick@1410ti,omap3-dss-interface-clock|Cx`uart4_fck@1000ti,wait-gate-clock|Sx`clockdomainscore_l3_clkdmti,clockdomain|dpll3_clkdmti,clockdomain|dpll1_clkdmti,clockdomain|per_clkdmti,clockdomainl|emu_clkdmti,clockdomain|jdpll4_clkdmti,clockdomain| wkup_clkdmti,clockdomain$|dss_clkdmti,clockdomain|core_l4_clkdmti,clockdomain|cam_clkdmti,clockdomain|iva2_clkdmti,clockdomain|dpll2_clkdmti,clockdomain|qd2d_clkdmti,clockdomain |dpll5_clkdmti,clockdomain|sgx_clkdmti,clockdomain|usbhost_clkdmti,clockdomain |target-module@48320000ti,sysc-omap2ti,syscxH2H2 revsysc|Qfckick+ H2counter@0ti,omap-counter32kx interrupt-controller@48200000ti,omap3-intcxH `target-module@48056000ti,sysc-omap2ti,syscxH`H`,H`(revsyscsyss#  |Mick+ H`dma-controller@0ti,omap3630-sdmati,omap-sdmax  ``gpio@48310000ti,omap3-gpioxH1gpio1+=M`gpio@49050000ti,omap3-gpioxIgpio2=M`gpio@49052000ti,omap3-gpioxI gpio3=M`gpio@49054000ti,omap3-gpioxI@ gpio4=Mgpio@49056000ti,omap3-gpioxI`!gpio5=Mgpio@49058000ti,omap3-gpioxI"gpio6=M`serial@4806a000ti,omap3-uartxH YH12txrxuart1lserial@4806c000ti,omap3-uartxHYI34txrxuart2lHdefaultVserial@49020000ti,omap3-uartxIYJn56txrxuart3lHdefaultVi2c@48070000 ti,omap3-i2cxH8txrx+i2c1HdefaultV'@twl@48xH  ti,twl4030HdefaultVaudioti,twl4030-audiocodecrtcti,twl4030-rtc bciti,twl4030-bci m{ vacwatchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1 ' regulator-vdacti,twl4030-vdacw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1:0`regulator-vmmc2ti,twl4030-vmmc2:0regulator-vusb1v5ti,twl4030-vusb1v5`regulator-vusb1v8ti,twl4030-vusb1v8`regulator-vusb3v1ti,twl4030-vusb3v1`regulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2w@w@regulator-vsimti,twl4030-vsimw@-gpioti,twl4030-gpio=Mtwl4030-usbti,twl4030-usb ` pwmti,twl4030-pwmpwmledti,twl4030-pwmled`pwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypadmadcti,twl4030-madc`i2c@48072000 ti,omap3-i2cxH 9txrx+i2c2 "disabledi2c@48060000 ti,omap3-i2cxH=txrx+i2c3HdefaultVeeprom@51 atmel,24c01xQ)lis33de@1dst,lis33dest,lis3lv02dx2=K]o   -x<xKZ&i&x "disabledmailbox@48094000ti,omap3-mailboxmailboxxH @dsp  spi@48098000ti,omap2-mcspixH A+mcspi1@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap2-mcspixH B+mcspi2 +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspixH [+mcspi3 tx0rx0tx1rx1spi@480ba000ti,omap2-mcspixH 0+mcspi4FGtx0rx01w@480b2000 ti,omap3-1wxH :hdq1wmmc@4809c000ti,omap3-hsmmcxH Smmc1=>txrxHdefaultVmmc@480b4000ti,omap3-hsmmcxH @Vmmc2/0txrxHdefaultV %mmc@480ad000ti,omap3-hsmmcxH ^mmc3MNtxrx "disabledmmu@480bd4003ti,omap2-iommuxH mmu_isp@` mmu@5d0000003ti,omap2-iommux]mmu_iva "disabledwdt@48314000 ti,omap3-wdtxH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspxH@mpu ;< Pcommontxrx`mcbsp1 txrx|fck "disabledtarget-module@480a0000ti,sysc-omap2ti,syscxH <H @H Drevsyscsyss|ick+ H rng@0 ti,omap2-rngx 4mcbsp@49022000ti,omap3-mcbspxI I mpusidetone>?Pcommontxrxsidetone`mcbsp2mcbsp2_sidetone!"txrx|fckick"okay`mcbsp@49024000ti,omap3-mcbspxI@I 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pwm-ledsoverovovero:blue:COM w5  mmc0soundti,omap-twl4030 overo hsusb2_power_regregulator-fixed hsusb2_vbusLK@LK@  p `hsusb2_phyusb-nop-xceiv % 1`regulator-w3cbw003c-npoweronregulator-fixedregulator-w3cbw003c-npoweron2Z2Z  `regulator-w3cbw003c-wifi-nresetHdefaultVregulator-fixed regulator-w3cbw003c-wifi-nreset2Z2Z  '`lis33-3v3-regregulator-fixedlis33-3v3-reg2Z2Z`lis33-1v8-regregulator-fixedlis33-1v8-regw@w@`regulator-vddvarioregulator-fixed vddvario <`regulator-vdd33aregulator-fixedvdd33a <` compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2serial3device_typeregclocksclock-namesclock-latencyoperating-points-v2vbb-supplyinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0phandlepinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftreg-namesti,sysc-maskti,sysc-sidleti,syss-maskdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyio-channelsio-channel-namesti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cellsstatuspagesizeVdd-supplyVdd_IO-supplyst,click-single-xst,click-single-yst,click-single-zst,click-thresh-xst,click-thresh-yst,click-thresh-zst,irq1-clickst,irq2-clickst,wakeup-x-lost,wakeup-x-hist,wakeup-y-lost,wakeup-y-hist,wakeup-z-lost,wakeup-z-hist,min-limit-xst,min-limit-yst,min-limit-zst,max-limit-xst,max-limit-yst,max-limit-z#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplybus-widthvqmmc-supplycap-sdio-irqnon-removable#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinslinux,mtd-namenand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelbank-widthgpmc,mux-add-datagpmc,oe-on-nsgpmc,we-on-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsenvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendturbo-modeti,absolute-max-voltage-uvpolling-delay-passivepolling-delaycoefficientsthermal-sensorspwmsmax-brightnesslinux,default-triggerti,modelti,mcbspgpiostartup-delay-usenable-active-highreset-gpiosvcc-supplyregulator-always-on