8h( @0Stechnexion,omap3-thundertechnexion,omap3-tao3530ti,omap3430ti,omap34xxti,omap3 +,7TI OMAP3 Thunder baseboard with TAO3530 SOMchosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000 d/displaycpus+cpu@0arm,cortex-a8mcpuy}cpupmu@54000000arm,cortex-a8-pmuyTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busyh +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-busy + pinmux@30 ti,omap3-padconfpinctrl-singley08+-pinmux_hsusbb2_pins`J          pinmux_mmc1_pinsPJ "$&^pinmux_mmc2_pins0J(*,.02^pinmux_wlan_gpioJ^pinmux_uart3_pinsJnAp^pinmux_i2c3_pinsJ^pinmux_mcspi1_pins J^pinmux_mcspi3_pins J^pinmux_mcbsp3_pins J<>@B^pinmux_twl4030_pinsJA^pinmux_dss_dpi_pinsJ^pinmux_lte430_pinsJ8^pinmux_backlight_pinsJ:^scm_conf@270sysconsimple-busyp0+ p0^pbias_regulator@2b0ti,pbias-omap3ti,pbias-omapyfpbias_mmc_omap2430mpbias_mmc_omap2430|w@-^clocks+mcbsp5_mux_fck@68ti,composite-mux-clock}yh^ mcbsp5_fckti,composite-clock} ^mcbsp1_mux_fck@4ti,composite-mux-clock}y^ mcbsp1_fckti,composite-clock} ^mcbsp2_mux_fck@4ti,composite-mux-clock} y^mcbsp2_fckti,composite-clock} ^mcbsp3_mux_fck@68ti,composite-mux-clock} yh^mcbsp3_fckti,composite-clock}^mcbsp4_mux_fck@68ti,composite-mux-clock} yh^mcbsp4_fckti,composite-clock}^clockdomainspinmux@a00 ti,omap3-padconfpinctrl-singley \+-pinmux_twl4030_vpins J^target-module@480a6000ti,sysc-omap2ti,syscyH `DH `HH `Lrevsyscsyss }ick+ H `  disabledaes1@0 ti,omap3-aesyP  txrxtarget-module@480c5000ti,sysc-omap2ti,syscyH PDH PHH PLrevsyscsyss }ick+ H P  disabledaes2@0 ti,omap3-aesyPABtxrxprm@48306000 ti,omap3-prmyH0`@ clocks+virt_16_8m_ck fixed-clockY^osc_sys_ck@d40 ti,mux-clock}y @^sys_ck@1270ti,divider-clock}yp)^!sys_clkout1@d70ti,gate-clock}y pdpll3_x2_ckfixed-factor-clock}@Kdpll3_m2x2_ckfixed-factor-clock}@K^ dpll4_x2_ckfixed-factor-clock}@Kcorex2_fckfixed-factor-clock} @K^"wkup_l4_ickfixed-factor-clock}!@K^Qcorex2_d3_fckfixed-factor-clock}"@K^corex2_d5_fckfixed-factor-clock}"@K^clockdomainscm@48004000 ti,omap3-cmyH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clock^Cvirt_12m_ck fixed-clock^virt_13m_ck fixed-clock]@^virt_19200000_ck fixed-clock$^virt_26000000_ck fixed-clock^virt_38_4m_ck fixed-clockI^dpll4_ck@d00ti,omap3-dpll-per-clock}!!y D 0^dpll4_m2_ck@d48ti,divider-clock}?y H)^#dpll4_m2x2_mul_ckfixed-factor-clock}#@K^$dpll4_m2x2_ck@d00ti,gate-clock}$y U^%omap_96m_alwon_fckfixed-factor-clock}%@K^,dpll3_ck@d00ti,omap3-dpll-core-clock}!!y @ 0^dpll3_m3_ck@1140ti,divider-clock}y@)^&dpll3_m3x2_mul_ckfixed-factor-clock}&@K^'dpll3_m3x2_ck@d00ti,gate-clock}' y U^(emu_core_alwon_ckfixed-factor-clock}(@K^esys_altclk fixed-clock^1mcbsp_clks fixed-clock^dpll3_m2_ck@d40ti,divider-clock}y @)^core_ckfixed-factor-clock}@K^)dpll1_fck@940ti,divider-clock})y @)^*dpll1_ck@904ti,omap3-dpll-clock}!*y  $ @ 4^dpll1_x2_ckfixed-factor-clock}@K^+dpll1_x2m2_ck@944ti,divider-clock}+y D)^?cm_96m_fckfixed-factor-clock},@K^-omap_96m_fck@d40 ti,mux-clock}-!y @^Hdpll4_m3_ck@e40ti,divider-clock} y@)^.dpll4_m3x2_mul_ckfixed-factor-clock}.@K^/dpll4_m3x2_ck@d00ti,gate-clock}/y U^0omap_54m_fck@d40 ti,mux-clock}01y @^;cm_96m_d2_fckfixed-factor-clock}-@K^2omap_48m_fck@d40 ti,mux-clock}21y @^3omap_12m_fckfixed-factor-clock}3@K^Jdpll4_m4_ck@e40ti,divider-clock}y@)^4dpll4_m4x2_mul_ckti,fixed-factor-clock}4ky^5dpll4_m4x2_ck@d00ti,gate-clock}5y U^dpll4_m5_ck@f40ti,divider-clock}?y@)^6dpll4_m5x2_mul_ckti,fixed-factor-clock}6ky^7dpll4_m5x2_ck@d00ti,gate-clock}7y U^mdpll4_m6_ck@1140ti,divider-clock}?y@)^8dpll4_m6x2_mul_ckfixed-factor-clock}8@K^9dpll4_m6x2_ck@d00ti,gate-clock}9y U^:emu_per_alwon_ckfixed-factor-clock}:@K^fclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock})y p^<clkout2_src_mux_ck@d70ti,composite-mux-clock})!-;y p^=clkout2_src_ckti,composite-clock}<=^>sys_clkout2@d70ti,divider-clock}>@y pmpu_ckfixed-factor-clock}?@K^@arm_fck@924ti,divider-clock}@y $emu_mpu_alwon_ckfixed-factor-clock}@@K^gl3_ick@a40ti,divider-clock})y @)^Al4_ick@a40ti,divider-clock}Ay @)^Brm_ick@c40ti,divider-clock}By @)gpt10_gate_fck@a00ti,composite-gate-clock}! y ^Dgpt10_mux_fck@a40ti,composite-mux-clock}C!y @^Egpt10_fckti,composite-clock}DEgpt11_gate_fck@a00ti,composite-gate-clock}! y ^Fgpt11_mux_fck@a40ti,composite-mux-clock}C!y @^Ggpt11_fckti,composite-clock}FGcore_96m_fckfixed-factor-clock}H@K^mmchs2_fck@a00ti,wait-gate-clock}y ^mmchs1_fck@a00ti,wait-gate-clock}y ^i2c3_fck@a00ti,wait-gate-clock}y ^i2c2_fck@a00ti,wait-gate-clock}y ^i2c1_fck@a00ti,wait-gate-clock}y ^mcbsp5_gate_fck@a00ti,composite-gate-clock} y ^mcbsp1_gate_fck@a00ti,composite-gate-clock} y ^ core_48m_fckfixed-factor-clock}3@K^Imcspi4_fck@a00ti,wait-gate-clock}Iy ^mcspi3_fck@a00ti,wait-gate-clock}Iy ^mcspi2_fck@a00ti,wait-gate-clock}Iy ^mcspi1_fck@a00ti,wait-gate-clock}Iy ^uart2_fck@a00ti,wait-gate-clock}Iy ^uart1_fck@a00ti,wait-gate-clock}Iy  ^core_12m_fckfixed-factor-clock}J@K^Khdq_fck@a00ti,wait-gate-clock}Ky ^core_l3_ickfixed-factor-clock}A@K^Lsdrc_ick@a10ti,wait-gate-clock}Ly ^gpmc_fckfixed-factor-clock}L@Kcore_l4_ickfixed-factor-clock}B@K^Mmmchs2_ick@a10ti,omap3-interface-clock}My ^mmchs1_ick@a10ti,omap3-interface-clock}My ^hdq_ick@a10ti,omap3-interface-clock}My ^mcspi4_ick@a10ti,omap3-interface-clock}My ^mcspi3_ick@a10ti,omap3-interface-clock}My ^mcspi2_ick@a10ti,omap3-interface-clock}My ^mcspi1_ick@a10ti,omap3-interface-clock}My ^i2c3_ick@a10ti,omap3-interface-clock}My ^i2c2_ick@a10ti,omap3-interface-clock}My ^i2c1_ick@a10ti,omap3-interface-clock}My ^uart2_ick@a10ti,omap3-interface-clock}My ^uart1_ick@a10ti,omap3-interface-clock}My  ^gpt11_ick@a10ti,omap3-interface-clock}My  ^gpt10_ick@a10ti,omap3-interface-clock}My  ^mcbsp5_ick@a10ti,omap3-interface-clock}My  ^mcbsp1_ick@a10ti,omap3-interface-clock}My  ^omapctrl_ick@a10ti,omap3-interface-clock}My ^dss_tv_fck@e00ti,gate-clock};y^dss_96m_fck@e00ti,gate-clock}Hy^dss2_alwon_fck@e00ti,gate-clock}!y^dummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock}!y ^Ngpt1_mux_fck@c40ti,composite-mux-clock}C!y @^Ogpt1_fckti,composite-clock}NO^aes2_ick@a10ti,omap3-interface-clock}My ^wkup_32k_fckfixed-factor-clock}C@K^Pgpio1_dbck@c00ti,gate-clock}Py ^sha12_ick@a10ti,omap3-interface-clock}My ^wdt2_fck@c00ti,wait-gate-clock}Py ^wdt2_ick@c10ti,omap3-interface-clock}Qy ^wdt1_ick@c10ti,omap3-interface-clock}Qy ^gpio1_ick@c10ti,omap3-interface-clock}Qy ^omap_32ksync_ick@c10ti,omap3-interface-clock}Qy ^gpt12_ick@c10ti,omap3-interface-clock}Qy ^gpt1_ick@c10ti,omap3-interface-clock}Qy ^per_96m_fckfixed-factor-clock},@K^ per_48m_fckfixed-factor-clock}3@K^Ruart3_fck@1000ti,wait-gate-clock}Ry ^gpt2_gate_fck@1000ti,composite-gate-clock}!y^Sgpt2_mux_fck@1040ti,composite-mux-clock}C!y@^Tgpt2_fckti,composite-clock}ST^gpt3_gate_fck@1000ti,composite-gate-clock}!y^Ugpt3_mux_fck@1040ti,composite-mux-clock}C!y@^Vgpt3_fckti,composite-clock}UVgpt4_gate_fck@1000ti,composite-gate-clock}!y^Wgpt4_mux_fck@1040ti,composite-mux-clock}C!y@^Xgpt4_fckti,composite-clock}WXgpt5_gate_fck@1000ti,composite-gate-clock}!y^Ygpt5_mux_fck@1040ti,composite-mux-clock}C!y@^Zgpt5_fckti,composite-clock}YZgpt6_gate_fck@1000ti,composite-gate-clock}!y^[gpt6_mux_fck@1040ti,composite-mux-clock}C!y@^\gpt6_fckti,composite-clock}[\gpt7_gate_fck@1000ti,composite-gate-clock}!y^]gpt7_mux_fck@1040ti,composite-mux-clock}C!y@^^gpt7_fckti,composite-clock}]^gpt8_gate_fck@1000ti,composite-gate-clock}! y^_gpt8_mux_fck@1040ti,composite-mux-clock}C!y@^`gpt8_fckti,composite-clock}_`gpt9_gate_fck@1000ti,composite-gate-clock}! y^agpt9_mux_fck@1040ti,composite-mux-clock}C!y@^bgpt9_fckti,composite-clock}abper_32k_alwon_fckfixed-factor-clock}C@K^cgpio6_dbck@1000ti,gate-clock}cy^gpio5_dbck@1000ti,gate-clock}cy^gpio4_dbck@1000ti,gate-clock}cy^gpio3_dbck@1000ti,gate-clock}cy^gpio2_dbck@1000ti,gate-clock}cy ^wdt3_fck@1000ti,wait-gate-clock}cy ^per_l4_ickfixed-factor-clock}B@K^dgpio6_ick@1010ti,omap3-interface-clock}dy^gpio5_ick@1010ti,omap3-interface-clock}dy^gpio4_ick@1010ti,omap3-interface-clock}dy^gpio3_ick@1010ti,omap3-interface-clock}dy^gpio2_ick@1010ti,omap3-interface-clock}dy ^wdt3_ick@1010ti,omap3-interface-clock}dy ^uart3_ick@1010ti,omap3-interface-clock}dy ^uart4_ick@1010ti,omap3-interface-clock}dy^gpt9_ick@1010ti,omap3-interface-clock}dy ^gpt8_ick@1010ti,omap3-interface-clock}dy ^gpt7_ick@1010ti,omap3-interface-clock}dy^gpt6_ick@1010ti,omap3-interface-clock}dy^gpt5_ick@1010ti,omap3-interface-clock}dy^gpt4_ick@1010ti,omap3-interface-clock}dy^gpt3_ick@1010ti,omap3-interface-clock}dy^gpt2_ick@1010ti,omap3-interface-clock}dy^mcbsp2_ick@1010ti,omap3-interface-clock}dy^mcbsp3_ick@1010ti,omap3-interface-clock}dy^mcbsp4_ick@1010ti,omap3-interface-clock}dy^mcbsp2_gate_fck@1000ti,composite-gate-clock}y^ mcbsp3_gate_fck@1000ti,composite-gate-clock}y^mcbsp4_gate_fck@1000ti,composite-gate-clock}y^emu_src_mux_ck@1140 ti,mux-clock}!efgy@^hemu_src_ckti,clkdm-gate-clock}h^ipclk_fck@1140ti,divider-clock}iy@)pclkx2_fck@1140ti,divider-clock}iy@)atclk_fck@1140ti,divider-clock}iy@)traceclk_src_fck@1140 ti,mux-clock}!efgy@^jtraceclk_fck@1140ti,divider-clock}j y@)secure_32k_fck fixed-clock^kgpt12_fckfixed-factor-clock}k@K^wdt1_fckfixed-factor-clock}k@Ksecurity_l4_ick2fixed-factor-clock}B@K^laes1_ick@a14ti,omap3-interface-clock}ly ^rng_ick@a14ti,omap3-interface-clock}ly ^sha11_ick@a14ti,omap3-interface-clock}ly des1_ick@a14ti,omap3-interface-clock}ly cam_mclk@f00ti,gate-clock}mycam_ick@f10!ti,omap3-no-wait-interface-clock}By^csi2_96m_fck@f00ti,gate-clock}y^security_l3_ickfixed-factor-clock}A@K^npka_ick@a14ti,omap3-interface-clock}ny icr_ick@a10ti,omap3-interface-clock}My des2_ick@a10ti,omap3-interface-clock}My mspro_ick@a10ti,omap3-interface-clock}My mailboxes_ick@a10ti,omap3-interface-clock}My ssi_l4_ickfixed-factor-clock}B@K^usr1_fck@c00ti,wait-gate-clock}!y ^ sr2_fck@c00ti,wait-gate-clock}!y ^sr_l4_ickfixed-factor-clock}B@Kdpll2_fck@40ti,divider-clock})y@)^odpll2_ck@4ti,omap3-dpll-clock}!oy$@4^pdpll2_m2_ck@44ti,divider-clock}pyD)^qiva2_ck@0ti,wait-gate-clock}qy^modem_fck@a00ti,omap3-interface-clock}!y ^sad2d_ick@a10ti,omap3-interface-clock}Ay ^mad2d_ick@a18ti,omap3-interface-clock}Ay ^mspro_fck@a00ti,wait-gate-clock}y ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock}"y ^rssi_ssr_div_fck_3430es2@a40ti,composite-divider-clock}"y @$^sssi_ssr_fck_3430es2ti,composite-clock}rs^tssi_sst_fck_3430es2fixed-factor-clock}t@K^hsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clock}Ly ^ssi_ick_3430es2@a10ti,omap3-ssi-interface-clock}uy ^usim_gate_fck@c00ti,composite-gate-clock}H y ^sys_d2_ckfixed-factor-clock}!@K^womap_96m_d2_fckfixed-factor-clock}H@K^xomap_96m_d4_fckfixed-factor-clock}H@K^yomap_96m_d8_fckfixed-factor-clock}H@K^zomap_96m_d10_fckfixed-factor-clock}H@K ^{dpll5_m2_d4_ckfixed-factor-clock}v@K^|dpll5_m2_d8_ckfixed-factor-clock}v@K^}dpll5_m2_d16_ckfixed-factor-clock}v@K^~dpll5_m2_d20_ckfixed-factor-clock}v@K^usim_mux_fck@c40ti,composite-mux-clock(}!wxyz{|}~y @)^usim_fckti,composite-clock}usim_ick@c10ti,omap3-interface-clock}Qy  ^dpll5_ck@d04ti,omap3-dpll-clock}!!y  $ L 4^dpll5_m2_ck@d50ti,divider-clock}y P)^vsgx_gate_fck@b00ti,composite-gate-clock})y ^core_d3_ckfixed-factor-clock})@K^core_d4_ckfixed-factor-clock})@K^core_d6_ckfixed-factor-clock})@K^omap_192m_alwon_fckfixed-factor-clock}%@K^core_d2_ckfixed-factor-clock})@K^sgx_mux_fck@b40ti,composite-mux-clock }-y @^sgx_fckti,composite-clock}^ sgx_ick@b10ti,wait-gate-clock}Ay ^cpefuse_fck@a08ti,gate-clock}!y ^ts_fck@a08ti,gate-clock}Cy ^usbtll_fck@a08ti,wait-gate-clock}vy ^usbtll_ick@a18ti,omap3-interface-clock}My ^mmchs3_ick@a10ti,omap3-interface-clock}My ^mmchs3_fck@a00ti,wait-gate-clock}y ^dss1_alwon_fck_3430es2@e00ti,dss-gate-clock}y^dss_ick_3430es2@e10ti,omap3-dss-interface-clock}By^usbhost_120m_fck@1400ti,gate-clock}vy^usbhost_48m_fck@1400ti,dss-gate-clock}3y^usbhost_ick@1410ti,omap3-dss-interface-clock}By^clockdomainscore_l3_clkdmti,clockdomain}dpll3_clkdmti,clockdomain}dpll1_clkdmti,clockdomain}per_clkdmti,clockdomainh}emu_clkdmti,clockdomain}idpll4_clkdmti,clockdomain}wkup_clkdmti,clockdomain$}dss_clkdmti,clockdomain}core_l4_clkdmti,clockdomain}cam_clkdmti,clockdomain}iva2_clkdmti,clockdomain}dpll2_clkdmti,clockdomain}pd2d_clkdmti,clockdomain }dpll5_clkdmti,clockdomain}sgx_clkdmti,clockdomain}usbhost_clkdmti,clockdomain }target-module@48320000ti,sysc-omap2ti,syscyH2H2 revsysc}Pfckick+ H2counter@0ti,omap-counter32ky interrupt-controller@48200000ti,omap3-intcyH ^target-module@48056000ti,sysc-omap2ti,syscyH`H`,H`(revsyscsyss#  }Lick+ H`dma-controller@0ti,omap3430-sdmati,omap-sdmay  `^gpio@48310000ti,omap3-gpioyH1gpio1.>gpio@49050000ti,omap3-gpioyIgpio2.>gpio@49052000ti,omap3-gpioyI gpio3.>gpio@49054000ti,omap3-gpioyI@ gpio4.>gpio@49056000ti,omap3-gpioyI`!gpio5.>^gpio@49058000ti,omap3-gpioyI"gpio6.>^ serial@4806a000ti,omap3-uartyH JH12txrxuart1lserial@4806c000ti,omap3-uartyHJI34txrxuart2lserial@49020000ti,omap3-uartyIJJ56txrxuart3l^defaultli2c@48070000 ti,omap3-i2cyH8txrx+i2c1'@twl@48yH  ti,twl4030^defaultlaudioti,twl4030-audiocodecrtcti,twl4030-rtc bciti,twl4030-bci v vacwatchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2 mvdd_ehci|w@w@regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1| ' ^regulator-vdacti,twl4030-vdac|w@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1|:0^regulator-vmmc2ti,twl4030-vmmc2|:0regulator-vusb1v5ti,twl4030-vusb1v5^regulator-vusb1v8ti,twl4030-vusb1v8^regulator-vusb3v1ti,twl4030-vusb3v1^regulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2|w@w@regulator-vsimti,twl4030-vsim|w@-^gpioti,twl4030-gpio.>^twl4030-usbti,twl4030-usb  ^pwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypad"2madcti,twl4030-madcE^i2c@48072000 ti,omap3-i2cyH 9txrx+i2c2i2c@48060000 ti,omap3-i2cyH=txrx+i2c3^defaultlmailbox@48094000ti,omap3-mailboxmailboxyH @Wcudsp  spi@48098000ti,omap2-mcspiyH A+mcspi1@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3^defaultlspidev@0spidevlyspi@4809a000ti,omap2-mcspiyH B+mcspi2 +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiyH [+mcspi3 tx0rx0tx1rx1^defaultlspidev@0spidevlyspi@480ba000ti,omap2-mcspiyH 0+mcspi4FGtx0rx01w@480b2000 ti,omap3-1wyH :hdq1wmmc@4809c000ti,omap3-hsmmcyH Smmc1=>txrx^defaultl mmc@480b4000ti,omap3-hsmmcyH @Vmmc2/0txrx^defaultl mmc@480ad000ti,omap3-hsmmcyH ^mmc3MNtxrx disabledmmu@480bd400-ti,omap2-iommuyH mmu_isp:^mmu@5d000000-ti,omap2-iommuy]mmu_iva disabledwdt@48314000 ti,omap3-wdtyH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspyH@mpu ;< JcommontxrxZmcbsp1 txrx}fck disabledtarget-module@480a0000ti,sysc-omap2ti,syscyH <H @H Drevsyscsyss}ick+ H rng@0 ti,omap2-rngy 4mcbsp@49022000ti,omap3-mcbspyI I mpusidetone>?JcommontxrxsidetoneZmcbsp2mcbsp2_sidetone!"txrx}fckickokay^mcbsp@49024000ti,omap3-mcbspyI@I mpusidetoneYZJcommontxrxsidetoneZmcbsp3mcbsp3_sidetonetxrx}fckickokay^defaultlmcbsp@49026000ti,omap3-mcbspyI`mpu 67 JcommontxrxZmcbsp4txrx}fcki disabledmcbsp@48096000ti,omap3-mcbspyH `mpu QR JcommontxrxZmcbsp5txrx}fck disabledsham@480c3000ti,omap3-shamshamyH 0d1Erx disabledtarget-module@48318000ti,sysc-omap2-timerti,syscyH1H1H1revsyscsyss' }fckick+ H1ztimer@0ti,omap3430-timery}fck%Ctarget-module@49032000ti,sysc-omap2-timerti,syscyI I I revsyscsyss' }fckick+ I timer@0ti,omap3430-timery&timer@49034000ti,omap3430-timeryI@'timer3timer@49036000ti,omap3430-timeryI`(timer4timer@49038000ti,omap3430-timeryI)timer5timer@4903a000ti,omap3430-timeryI*timer6timer@4903c000ti,omap3430-timeryI+timer7timer@4903e000ti,omap3430-timeryI,timer8timer@49040000ti,omap3430-timeryI-timer9timer@48086000ti,omap3430-timeryH`.timer10timer@48088000ti,omap3430-timeryH/timer11target-module@48304000ti,sysc-omap2-timerti,syscyH0@H0@H0@revsyscsyss' }fckick+ H0@timer@0ti,omap3430-timery_usbhstll@48062000 ti,usbhs-tllyH N usb_tll_hsusbhshost@48064000ti,usbhs-hostyH@ usb_host_hs+ ehci-phyohci@48064400ti,ohci-omap3yHDLehci@48064800 ti,ehci-omapyHHMgpmc@6e000000ti,omap3430-gpmcgpmcynrxtx!-+.>0^nand@0,0ti,omap2-nand y ?N`swp~$$$0H"H36B+x-loader@0 TX-Loaderybootloaders@80000TU-Bootybootloaders_env@260000 TU-Boot Envy&kernel@280000TKernely(@filesystem@680000 TFile Systemyhusb_otg_hs@480ab000ti,omap3-musbyH \]Jmcdma usb_otg_hsZem v usb2-phy2dss@48050000 ti,omap3-dssyHok dss_core}fck+^defaultldispc@48050400ti,omap3-dispcyH dss_dispc}fckencoder@4804fc00 ti,omap3-dsiyHH@H protophypll disabled dss_dsi1} fcksys_clkencoder@48050800ti,omap3-rfbiyH disabled dss_rfbi}fckickencoder@48050c00ti,omap3-vencyH  disabled dss_venc}fckportendpoint^ssi-controller@48058000 ti,omap3-ssissiokyHHsysgddGJgdd_mpu+ }t ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portyHHtxrxCDssi-port@4805b000ti,omap3-ssi-portyHHtxrxEFpinmux@480025d8 ti,omap3-padconfpinctrl-singleyH%$+-isp@480bc000 ti,omap3-ispyH H |flports+bandgap@48002524yH%$ti,omap34xx-bandgap^ target-module@480cb000ti,sysc-omap3430-srti,syscsmartreflex_coreyH $sysc}fck+ H smartreflex@0ti,omap3-smartreflex-coreytarget-module@480c9000ti,sysc-omap3430-srti,syscsmartreflex_mpu_ivayH $sysc} fck+ H smartreflex@480c9000ti,omap3-smartreflex-mpu-ivaytarget-module@50000000ti,sysc-omap2ti,syscyPrev} fckick+ P@opp-tableoperating-points-v2-ti-cpuf^opp1-125000000sY@ opp2-250000000沀 g8g8g8opp3-500000000e OOOopp4-550000000 U txtxtxopp5-600000000#F pppopp6-720000000*T pppthermal-zonescpu_thermal4BN O memory@80000000mmemoryyhsusb2_power_regregulator-fixed mhsusb2_vbus|2Z2Z _dp^ hsusb2_phyusb-nop-xceiv u   ^soundti,omap-twl4030 omap3beagleregulator-mmc2-sdio-poweronregulator-fixedmregulator-mmc2-sdio-poweron|00 _d'^displaysamsung,lte430wq-f0cpanel-dpiTlcd^defaultl  portendpoint^panel-timingT@*     %backlightgpio-backlight^defaultl   5 compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-points-v2cpu0-supplyinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinsphandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftreg-namesti,sysc-maskti,sysc-sidleti,syss-maskstatusdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0bci3v1-supplyio-channelsio-channel-namesregulator-always-onti,use-ledsti,pullupsti,pulldownsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencyspi-cphati,dual-voltpbias-supplyvmmc-supplyvqmmc-supplycd-gpiosbus-widthnon-removablecap-power-off-card#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,wr-access-nslabelmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerremote-endpointdata-linesiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendturbo-modepolling-delay-passivepolling-delaycoefficientsthermal-sensorsgpiostartup-delay-usreset-gpiosvcc-supplyti,modelti,mcbspenable-gpioshactivevactivehfront-porchhback-porchhsync-lenvback-porchvfront-porchvsync-lenhsync-activevsync-activede-activepixelclk-activedefault-on