N88E ( DCvariscite,var-dvk-om44variscite,var-som-om44ti,omap4460ti,omap4 +7Variscite VAR-DVK-OM44chosenaliases?=/ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0?B/ocp/interconnect@48000000/segment@0/target-module@72000/i2c@0?G/ocp/interconnect@48000000/segment@0/target-module@60000/i2c@0EL/ocp/interconnect@48000000/segment@200000/target-module@150000/i2c@0BQ/ocp/interconnect@48000000/segment@0/target-module@6a000/serial@0BY/ocp/interconnect@48000000/segment@0/target-module@6c000/serial@0Ba/ocp/interconnect@48000000/segment@0/target-module@20000/serial@0Bi/ocp/interconnect@48000000/segment@0/target-module@6e000/serial@0 q/ocp/dspx/ocp/ipu@55020000 /display /connectorcpus+cpu@0arm,cortex-a9cpucpuW0 `O cpu@1arm,cortex-a9cpupmuarm,cortex-a9-pmudebugss67interrupt-controller@48241000arm,cortex-a9-gic%H$H$ cache-controller@48242000arm,pl310-cacheH$ 6Dlocal-timer@48240600arm,cortex-a9-twd-timerH$    interrupt-controller@48281000ti,omap4-wugen-mpu%H( socti,omap-inframpu ti,omap4-mpumpuPiva ti,ivahdivaocpti,omap4-l3-nocsimple-bus+Ul3_main_1l3_main_2l3_main_3DD E  interconnect@4a300000ti,omap4-l4-wkupsimple-busJ0J0J0 \aplaia0+$UJ0J1J2segment@0 simple-bus+U`` @@PPtarget-module@4000ti,sysc-omap2ti,sysc@@ \revsyscf 0fck+ U@counter@0ti,omap-counter32k target-module@6000ti,sysc-omap4ti,sysc`\rev+ U` prm@0ti,omap4-prmsimple-bus   + U clocks+sys_clkin_ck@110t ti,mux-clock abe_dpll_bypass_clk_mux_ck@108t ti,mux-clock7abe_dpll_refclk_mux_ck@10ct ti,mux-clock 6dbgclk_mux_cktfixed-factor-clockl4_wkup_clk_mux_ck@108t ti,mux-clocksyc_clk_div_ck@100tti,divider-clockusim_ck@1858tti,divider-clockXusim_fclk@1858tti,gate-clockXtrace_clk_div_cktti,clkdm-gate-clock div_ts_ck@1888tti,divider-clock  bandgap_ts_fclk@1888tti,gate-clockclockdomainsemu_sys_clkdmti,clockdomainl4_wkup_cm@1800 ti,omap4-cm+ Uclk@20 ti,clkctrl \temu_sys_cm@1a00 ti,omap4-cm+ Uclk@20 ti,clkctrl tprm@400#ti,omap4-prm-instti,omap-prm-instbprm@700#ti,omap4-prm-instti,omap-prm-instprm@f00#ti,omap4-prm-instti,omap-prm-instprm@1b00#ti,omap4-prm-instti,omap-prm-inst@target-module@a000ti,sysc-omap4ti,sysc\rev+ Uscrm@0ti,omap4-scrm clocks+auxclk0_src_gate_ck@310t ti,composite-no-wait-gate-clockauxclk0_src_mux_ck@310tti,composite-mux-clock auxclk0_src_cktti,composite-clockauxclk0_ck@310tti,divider-clock,auxclk1_src_gate_ck@314t ti,composite-no-wait-gate-clockauxclk1_src_mux_ck@314tti,composite-mux-clock auxclk1_src_cktti,composite-clockauxclk1_ck@314tti,divider-clock-auxclk2_src_gate_ck@318t ti,composite-no-wait-gate-clock auxclk2_src_mux_ck@318tti,composite-mux-clock !auxclk2_src_cktti,composite-clock !"auxclk2_ck@318tti,divider-clock".auxclk3_src_gate_ck@31ct ti,composite-no-wait-gate-clock#auxclk3_src_mux_ck@31ctti,composite-mux-clock $auxclk3_src_cktti,composite-clock#$%auxclk3_ck@31ctti,divider-clock%/auxclk4_src_gate_ck@320t ti,composite-no-wait-gate-clock &auxclk4_src_mux_ck@320tti,composite-mux-clock  'auxclk4_src_cktti,composite-clock&'(auxclk4_ck@320tti,divider-clock( 0auxclk5_src_gate_ck@324t ti,composite-no-wait-gate-clock$)auxclk5_src_mux_ck@324tti,composite-mux-clock $*auxclk5_src_cktti,composite-clock)*+auxclk5_ck@324tti,divider-clock+$1auxclkreq0_ck@210t ti,mux-clock,-./01auxclkreq1_ck@214t ti,mux-clock,-./01auxclkreq2_ck@218t ti,mux-clock,-./01auxclkreq3_ck@21ct ti,mux-clock,-./01auxclkreq4_ck@220t ti,mux-clock,-./01 auxclkreq5_ck@224t ti,mux-clock,-./01$clockdomainstarget-module@c000ti,sysc-omap4ti,syscctrl_module_wkup \revsyscf+ Uscm@c000ti,omap4-scm-wkupsegment@10000 simple-bus+xU@@PPtarget-module@0ti,sysc-omap2ti,sysc\revsyscsyssf fckdbclk+ Ugpio@0ti,omap4-gpio  %target-module@4000ti,sysc-omap2ti,sysc@@@\revsyscsyss"f fck+ U@wdt@0ti,omap4-wdtti,omap3-wdt Ptarget-module@8000ti,sysc-omap2-timerti,sysc\revsyscsyss' f  fck+ U&:timer@0ti,omap3430-timer fcktimer_sys_ck %E T dtarget-module@c000ti,sysc-omap2ti,sysc\revsyscsyss' f Xfck+ Ukeypad@0ti,omap4-keypad x\mpu {disabledtarget-module@e000ti,sysc-omap4ti,syscctrl_module_pad_wkup \revsyscf+ Upinmux@40 ti,omap4-padconfpinctrl-single@8+%default23pinmux_hsusbb1_phy_clk_pinspinmux_hsusbb1_hub_rst_pins2pinmux_lan7500_rst_pins3pinmux_twl6030_wkup_pinsvsegment@20000 simple-bus+U``  00@@PPpptarget-module@0ti,sysc {disabled+ Utarget-module@2000ti,sysc {disabled+ U target-module@4000ti,sysc {disabled+ U@target-module@6000ti,sysc {disabled+0U`p 0interconnect@4a000000ti,omap4-l4-cfgsimple-busJJJ \aplaia0+TUJJJJ J (J(0J0segment@0 simple-bus+U 00@@PP``pp@  00 ``pp @@PPtarget-module@2000ti,sysc-omap4ti,syscctrl_module_core   \revsyscf+ U scm@0ti,omap4-scm-coresimple-bus+ Uscm_conf@0syscon+control-phy@300ti,control-phy-usb2\powerecontrol-phy@33cti,control-phy-otghs<\otghs_controldtarget-module@4000ti,sysc-omap4ti,sysc@\rev+ U@cm1@0ti,omap4-cm1simple-bus + U clocks+extalt_clkin_ckt fixed-clockDpad_clks_src_ckt fixed-clock4pad_clks_ck@108tti,gate-clock4pad_slimbus_core_clks_ckt fixed-clocksecure_32k_clk_src_ckt fixed-clockslimbus_src_clkt fixed-clock5slimbus_clk@108tti,gate-clock5 sys_32k_ckt fixed-clockvirt_12000000_ckt fixed-clockvirt_13000000_ckt fixed-clock]@ virt_16800000_ckt fixed-clockY virt_19200000_ckt fixed-clock$ virt_26000000_ckt fixed-clock virt_27000000_ckt fixed-clock virt_38400000_ckt fixed-clockItie_low_clock_ckt fixed-clockutmi_phy_clkout_ckt fixed-clockxclk60mhsp1_ckt fixed-clock^xclk60mhsp2_ckt fixed-clock_xclk60motg_ckt fixed-clockdpll_abe_ck@1e0tti,omap4-dpll-m4xen-clock678dpll_abe_x2_ck@1f0tti,omap4-dpll-x2-clock89dpll_abe_m2x2_ck@1f0tti,divider-clock9:abe_24m_fclktfixed-factor-clock:abe_clk@108tti,divider-clock:1dpll_abe_m3x2_ck@1f4tti,divider-clock9;core_hsd_byp_clk_mux_ck@12ct ti,mux-clock;,<dpll_core_ck@120tti,omap4-dpll-core-clock< $,(=dpll_core_x2_cktti,omap4-dpll-x2-clock=>dpll_core_m6x2_ck@140tti,divider-clock>@dpll_core_m2_ck@130tti,divider-clock=0?ddrphy_cktfixed-factor-clock?dpll_core_m5x2_ck@13ctti,divider-clock><@div_core_ck@100tti,divider-clock@Kdiv_iva_hs_clk@1dctti,divider-clock@1Ddiv_mpu_hs_clk@19ctti,divider-clock@1Jdpll_core_m4x2_ck@138tti,divider-clock>8Adll_clk_div_cktfixed-factor-clockAdpll_abe_m2_ck@1f0tti,divider-clock8Ndpll_core_m3x2_gate_ck@134t ti,composite-no-wait-gate-clock>4Bdpll_core_m3x2_div_ck@134tti,composite-divider-clock>4Cdpll_core_m3x2_cktti,composite-clockBCdpll_core_m7x2_ck@144tti,divider-clock>Diva_hsd_byp_clk_mux_ck@1act ti,mux-clockDEdpll_iva_ck@1a0tti,omap4-dpll-clockETFG7Fdpll_iva_x2_cktti,omap4-dpll-x2-clockFGdpll_iva_m4x2_ck@1b8tti,divider-clockGTHG~Hdpll_iva_m5x2_ck@1bctti,divider-clockGTIG] Idpll_mpu_ck@160tti,omap4-dpll-clockJ`dlhdpll_mpu_m2_ck@170tti,divider-clockpper_hs_clk_div_cktfixed-factor-clock;Ousb_hs_clk_div_cktfixed-factor-clock;Ul3_div_ck@100tti,divider-clockKLl4_div_ck@100tti,divider-clockLlp_clk_div_cktfixed-factor-clock:mpu_periphclktfixed-factor-clockocp_abe_iclk@528tti,divider-clock M(per_abe_24m_fclktfixed-factor-clockNdummy_ckt fixed-clockclockdomainsmpuss_cm@300 ti,omap4-cm+ Uclk@20 ti,clkctrl ttesla_cm@400 ti,omap4-cm+ Uclk@20 ti,clkctrl taabe_cm@500 ti,omap4-cm+ Uclk@20 ti,clkctrl ltMtarget-module@8000ti,sysc-omap4ti,sysc\rev+ U cm2@0ti,omap4-cm2simple-bus + U clocks+per_hsd_byp_clk_mux_ck@14ct ti,mux-clockOLPdpll_per_ck@140tti,omap4-dpll-clockP@DLHQdpll_per_m2_ck@150tti,divider-clockQPYdpll_per_x2_ck@150tti,omap4-dpll-x2-clockQPRdpll_per_m2x2_ck@150tti,divider-clockRPXdpll_per_m3x2_gate_ck@154t ti,composite-no-wait-gate-clockRTSdpll_per_m3x2_div_ck@154tti,composite-divider-clockRTTdpll_per_m3x2_cktti,composite-clockSTdpll_per_m4x2_ck@158tti,divider-clockRXdpll_per_m5x2_ck@15ctti,divider-clockR\dpll_per_m6x2_ck@160tti,divider-clockR`Wdpll_per_m7x2_ck@164tti,divider-clockRddpll_usb_ck@180tti,omap4-dpll-j-type-clockUVdpll_usb_clkdcoldo_ck@1b4tti,fixed-factor-clockV\idpll_usb_m2_ck@190tti,divider-clockVZducati_clk_mux_ck@100t ti,mux-clockKWfunc_12m_fclktfixed-factor-clockXfunc_24m_clktfixed-factor-clockYfunc_24mc_fclktfixed-factor-clockXfunc_48m_fclk@108tti,divider-clockXfunc_48mc_fclktfixed-factor-clockXfunc_64m_fclk@108tti,divider-clockfunc_96m_fclk@108tti,divider-clockXinit_60m_fclk@104tti,divider-clockZ]per_abe_nc_fclk@108tti,divider-clockNsha2md5_fck@15c8tti,gate-clockLusb_phy_cm_clk32k@640tti,gate-clock@fclockdomainsl3_init_clkdmti,clockdomainVl4_ao_cm@600 ti,omap4-cm+ Uclk@20 ti,clkctrl thl3_1_cm@700 ti,omap4-cm+ Uclk@20 ti,clkctrl tl3_2_cm@800 ti,omap4-cm+ Uclk@20 ti,clkctrl tducati_cm@900 ti,omap4-cm + U clk@20 ti,clkctrl tl3_dma_cm@a00 ti,omap4-cm + U clk@20 ti,clkctrl t[l3_emif_cm@b00 ti,omap4-cm + U clk@20 ti,clkctrl td2d_cm@c00 ti,omap4-cm + U clk@20 ti,clkctrl tgl4_cfg_cm@d00 ti,omap4-cm + U clk@20 ti,clkctrl til3_instr_cm@e00 ti,omap4-cm+ Uclk@20 ti,clkctrl $tivahd_cm@f00 ti,omap4-cm+ Uclk@20 ti,clkctrl tiss_cm@1000 ti,omap4-cm+ Uclk@20 ti,clkctrl tll3_dss_cm@1100 ti,omap4-cm+ Uclk@20 ti,clkctrl tl3_gfx_cm@1200 ti,omap4-cm+ Uclk@20 ti,clkctrl tl3_init_cm@1300 ti,omap4-cm+ Uclk@20 ti,clkctrl t\l4_per_cm@1400 ti,omap4-cm+ Uclock@20ti,clkctrl-l4-perti,clkctrl Dtmclock@1a0 ti,clkctrl-l4-secureti,clkctrl<t|target-module@56000ti,sysc-omap2ti,sysc``,`(\revsyscsyss# w f [fck+ U`dma-controller@0ti,omap4430-sdmati,omap-sdma0   }target-module@58000ti,sysc-omap2ti,sysc\revsyscsyss#wf \fck+ UPhsi@0 ti,omap4-hsi@P\sysgdd \hsi_fck Ggdd_mpu+ U@hsi-port@2000ti,omap4-hsi-port (\txrx Chsi-port@3000ti,omap4-hsi-port08\txrx Dtarget-module@5e000ti,sysc {disabled+ U target-module@62000ti,sysc-omap2ti,sysc   \revsyscsyss f \Hfck+ U usbhstll@0 ti,usbhs-tll Ntarget-module@64000ti,sysc-omap4ti,sysc@@@\revsyscsysswf \8fck+ U@usbhshost@0ti,usbhs-host+ U ]^_3refclk_60m_intrefclk_60m_ext_p1refclk_60m_ext_p2 ehci-phyohci@800ti,ohci-omap3 Lehci@c00 ti,ehci-omap  M`target-module@66000ti,sysc-omap2ti,sysc```\revsyscsyss f afckbrstctrl+ U`mmu@0ti,omap4-iommu segment@80000 simple-bus+U      @@PP``pp` `p p        target-module@29000ti,sysc {disabled+ Utarget-module@2b000ti,sysc-omap2ti,sysc\revsyscsyss wf \@fck+ Uusb_otg_hs@0ti,omap4-musb\]mcdmacc  usb2-phy' 0d<K2target-module@2d000ti,sysc-omap2ti,sysc\revsyscsyss f \fck+ Uocp2scp@0ti,omap-ocp2scp+ Uusb2phy@80 ti,omap-usb2X0efwkupclkQctarget-module@36000ti,sysc-omap2ti,sysc```\revsyscsyssf gfck+ U`target-module@4d000ti,sysc-omap2ti,sysc\revsyscsyssf gfck+ Utarget-module@59000ti,sysc-omap4-srti,sysc8\syscf hfck+ Usmartreflex@0ti,omap4-smartreflex-mpu target-module@5b000ti,sysc-omap4-srti,sysc8\syscf hfck+ Usmartreflex@0ti,omap4-smartreflex-iva ftarget-module@5d000ti,sysc-omap4-srti,sysc8\syscf hfck+ Usmartreflex@0ti,omap4-smartreflex-core target-module@60000ti,sysc {disabled+ Utarget-module@74000ti,sysc-omap4ti,sysc@@ \revsysc f ifck+ U@mailbox@0ti,omap4-mailbox \hzmbox_ipu  mbox_dsp  target-module@76000ti,sysc-omap2ti,sysc```\revsyscsyss f ifck+ U`spinlock@0ti,omap4-hwspinlocksegment@100000 simple-bus+`U  00target-module@0ti,sysc-omap4ti,syscctrl_module_pad_core \revsyscf+ Upinmux@40 ti,omap4-padconfpinctrl-single@+%defaultjpinmux_mcpdm_pins(pinmux_twl6040_pins\`xpinmux_tsc2004_pinsPRppinmux_uart3_pins npinmux_hsusbb1_pins`           jpinmux_hsusbb1_phy_rst_pinsLpinmux_i2c1_pinstpinmux_i2c3_pinsopinmux_mmc1_pins0pinmux_twl6030_pins^Aupinmux_uart2_pins spinmux_wl12xx_ctrl_pins"$&pinmux_mmc4_pins0pinmux_uart1_pins rpinmux_mcspi1_pins ~pinmux_mcsasp_pinspinmux_dss_dpi_pins"$&(*,.0246tvxz|~pinmux_dss_hdmi_pinsZ\^pinmux_i2c4_pinspinmux_mmc5_pins8  pinmux_gpio_led_pins>@pinmux_gpio_key_pinsbpinmux_ks8851_irq_pins<pinmux_hdmi_hpd_pinsX pinmux_backlight_pinsomap4_padconf_global@5a0sysconsimple-busp+ Upkpbias_regulator@60ti,pbias-omap4ti,pbias-omap`kpbias_mmc_omap4pbias_mmc_omap4w@-target-module@2000ti,sysc {disabled+ U target-module@8000ti,sysc {disabled+ Utarget-module@a000ti,sysc-omap4ti,sysc \revsysc w f lfck+ Usegment@180000 simple-bus+segment@200000 simple-bus+hU!!  @ @P P` `p p ! 0!0  !!`!`p!p@!@P!P!!""`"`p"p""""!!target-module@4000ti,sysc {disabled+ U@target-module@6000ti,sysc {disabled+ U`target-module@a000ti,sysc {disabled+ Utarget-module@c000ti,sysc {disabled+ Utarget-module@10000ti,sysc {disabled+ Utarget-module@12000ti,sysc {disabled+ U target-module@14000ti,sysc {disabled+ U@target-module@16000ti,sysc {disabled+ U`target-module@18000ti,sysc {disabled+ Utarget-module@1c000ti,sysc {disabled+ Utarget-module@1e000ti,sysc {disabled+ Utarget-module@20000ti,sysc {disabled+ Utarget-module@26000ti,sysc {disabled+ U`target-module@28000ti,sysc {disabled+ Utarget-module@2a000ti,sysc {disabled+ Usegment@280000 simple-bus+segment@300000 simple-bus+U042@@2@ `2`p2p2232 2@11@1 1 target-module@0ti,sysc {disabled+U@  @@@ ``pp @interconnect@48000000ti,omap4-l4-persimple-bus0HHHHHH\aplaia0ia1ia2ia3+UH H segment@0 simple-bus+U  00@@PP``ppPP``pp  00 ` ` p p``pp``pp             @ @ ` ` @     0 0 @ @ P P        P P ` `  0 0 P Ptarget-module@20000ti,sysc-omap2ti,syscPTX\revsyscsyssf m0fck+ Userial@0ti,omap4-uart Jldefaultn{okaytarget-module@32000ti,sysc-omap2-timerti,sysc   \revsyscsyss' f mfck+ U timer@0ti,omap3430-timermfcktimer_sys_ck &target-module@34000ti,sysc-omap4-timerti,sysc@@ \revsyscf m fck+ U@timer@0ti,omap4430-timerm fcktimer_sys_ck 'target-module@36000ti,sysc-omap4-timerti,sysc`` \revsyscf m(fck+ U`timer@0ti,omap4430-timerm(fcktimer_sys_ck (target-module@3e000ti,sysc-omap4-timerti,sysc \revsyscf m0fck+ Utimer@0ti,omap4430-timerm0fcktimer_sys_ck -target-module@40000ti,sysc {disabled+ Utarget-module@55000ti,sysc-omap2ti,syscPPQ\revsyscsyssfm@m@ fckdbclk+ UPgpio@0ti,omap4-gpio  %target-module@57000ti,sysc-omap2ti,syscppq\revsyscsyssfmHmH fckdbclk+ Upgpio@0ti,omap4-gpio  %target-module@59000ti,sysc-omap2ti,sysc\revsyscsyssfmPmP fckdbclk+ Ugpio@0ti,omap4-gpio   %qtarget-module@5b000ti,sysc-omap2ti,sysc\revsyscsyssfmXmX fckdbclk+ Ugpio@0ti,omap4-gpio ! %target-module@5d000ti,sysc-omap2ti,sysc\revsyscsyssfm`m` fckdbclk+ Ugpio@0ti,omap4-gpio " %ytarget-module@60000ti,sysc-omap2ti,sysc\revsyscsyssf mfck+ Ui2c@0 ti,omap4-i2c =+defaulto{okaytsc2004@48 ti,tsc2004Hdefaultp q {disabledtmp105@49 ti,tmp105Ieeprom@50microchip,24c32atmel,24c32Ptarget-module@6a000ti,sysc-omap2ti,syscPTX\revsyscsyssf m fck+ Userial@0ti,omap4-uart Hl{okaydefaultrtarget-module@6c000ti,sysc-omap2ti,syscPTX\revsyscsyssf m(fck+ Userial@0ti,omap4-uart Il{okaydefaultstarget-module@6e000ti,sysc-omap2ti,syscPTX\revsyscsyssf m8fck+ Userial@0ti,omap4-uart Fl {disabledtarget-module@70000ti,sysc-omap2ti,sysc\revsyscsyssf mfck+ Ui2c@0 ti,omap4-i2c 8+defaultt{okaytwl@48H  ti,twl6030%defaultuvrtcti,twl4030-rtc regulator-vaux1ti,twl6030-vaux1B@-regulator-vaux2ti,twl6030-vaux2O*regulator-vaux3ti,twl6030-vaux3B@-regulator-vmmcti,twl6030-vmmcO-regulator-vppti,twl6030-vppw@&%regulator-vusimti,twl6030-vusim--regulator-vdacti,twl6030-vdacregulator-vanati,twl6030-vanaregulator-vcxioti,twl6030-vcxioregulator-vusbti,twl6030-vusbwregulator-v1v8ti,twl6030-v1v8zregulator-v2v1ti,twl6030-v2v1{usb-comparatorti,twl6030-usb (wpwmti,twl6030-pwm3pwmledti,twl6030-pwmled3gpadcti,twl6030-gpadc>twl@4b ti,twl6040tKdefaultx w Pyazl{xtarget-module@72000ti,sysc-omap2ti,sysc   \revsyscsyssf mfck+ U i2c@0 ti,omap4-i2c 9+ {disabledtarget-module@76000ti,sysc-omap4ti,sysc`` \revsyscf mfck+ U`target-module@78000ti,sysc-omap2ti,sysc\revsyscsyss f m8fck+ Uelm@0ti,am3352-elm   {disabledtarget-module@86000ti,sysc-omap2-timerti,sysc```\revsyscsyss' f mfck+ U`timer@0ti,omap3430-timermfcktimer_sys_ck .target-module@88000ti,sysc-omap4-timerti,sysc \revsyscf mfck+ Utimer@0ti,omap4430-timermfcktimer_sys_ck /target-module@90000ti,sysc-omap2ti,sysc   \revsyscf | fck+ U rng@0 ti,omap4-rng  4target-module@96000ti,sysc-omap2ti,sysc `\sysc f mfck+ U `mcbsp@0ti,omap4-mcbsp\mpu common}} txrx {disabledtarget-module@98000ti,sysc-omap4ti,sysc   \revsyscf mfck+ U spi@0ti,omap4-mcspi A+@}#}$}%}&}'}(})}* tx0rx0tx1rx1tx2rx2tx3rx3{okaydefault~eth@0ks8851defaultn6 y target-module@9a000ti,sysc-omap4ti,sysc   \revsyscf mfck+ U spi@0ti,omap4-mcspi B+ }+},}-}.tx0rx0tx1rx1 {disabledtarget-module@9c000ti,sysc-omap4ti,sysc   \revsyscwf \fck+ U mmc@0ti,omap4-hsmmc S}=}>txrxdefault{okaytarget-module@9e000ti,sysc {disabled+ U target-module@a2000ti,sysc {disabled+ U target-module@a4000ti,sysc {disabled+U @ Ptarget-module@a5000ti,sysc-omap2ti,sysc P0 P4 P8\revsyscsyssf |fck+ U Pdes@0 ti,omap4-des R}u}ttxrxtarget-module@a8000ti,sysc {disabled+ U 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I0I0I@I@IPIPI`I`IpIpIIIIIIIIIIIIIIIII I I0I0IIIIIIIIIIIIIIIIIIIII I I I I I I I III I target-module@22000ti,sysc-omap2ti,sysc \sysc f M(fck+U I I mcbsp@0ti,omap4-mcbspI \mpudma common}!}"txrx {disabledtarget-module@24000ti,sysc-omap2ti,sysc@\sysc f M0fck+U@I@I@mcbsp@0ti,omap4-mcbspI@\mpudma common}}txrx {disabledtarget-module@26000ti,sysc-omap2ti,sysc`\sysc f M8fck+U`I`I`mcbsp@0ti,omap4-mcbspI`\mpudma common}}txrx {disabledtarget-module@28000ti,sysc-mcaspti,sysc \revsyscf M fck+UIItarget-module@2a000ti,sysc {disabled+UIItarget-module@2e000ti,sysc-omap4ti,sysc \revsyscf Mfck+UIIdmic@0ti,omap4-dmicI\mpudma r}Cup_link {disabledtarget-module@30000ti,sysc-omap2ti,sysc\revsyscsyss"f Mhfck+UIIwdt@0ti,omap4-wdtti,omap3-wdt Ptarget-module@32000ti,sysc-omap4ti,sysc   \revsyscf Mfck+U I I {okaydefaultmcpdm@0ti,omap4-mcpdmI \mpudma p}A}Bup_linkdn_linkpdmclktarget-module@38000ti,sysc-omap4-timerti,sysc \revsyscf MHfck+UIItimer@0ti,omap4430-timerIMHfcktimer_sys_ck )Qtarget-module@3a000ti,sysc-omap4-timerti,sysc \revsyscf MPfck+UIItimer@0ti,omap4430-timerIMPfcktimer_sys_ck *Qtarget-module@3c000ti,sysc-omap4-timerti,sysc \revsyscf MXfck+UIItimer@0ti,omap4430-timerIMXfcktimer_sys_ck +Qtarget-module@3e000ti,sysc-omap4-timerti,sysc \revsyscf M`fck+UIItimer@0ti,omap4430-timerIM`fcktimer_sys_ck ,Qtarget-module@80000ti,sysc {disabled+UIItarget-module@a0000ti,sysc {disabled+U I I target-module@c0000ti,sysc {disabled+U I I target-module@f1000ti,sysc-omap4ti,sysc \revsyscw f Mfck+UIIsram@40304000 mmio-sram@0@gpmc@50000000ti,omap4430-gpmcP+ }rxtx^jgpmc|Lfck%  {disabledtarget-module@52000000ti,sysc-omap4ti,syscissRR \revsyscwf lfck+ URtarget-module@55082000ti,sysc-omap2ti,syscU U U \revsyscsyss f fckrstctrl UU +mmu@0ti,omap4-iommu dtarget-module@4012c000ti,sysc-omap4ti,sysc@@ \revsyscf M@fck+U@IIdmm@4e000000 ti,omap4-dmmN qdmmemif@4c000000 ti,emif-4dL nemif1|emif@4d000000 ti,emif-4dM oemif2|dsp ti,omap4-dsp b aomap4-dsp-fw.xe64T  {disabledipu@55020000 ti,omap4-ipuU\l2ram omap4-ipu-fw.xem3  {disabledtarget-module@4b501000ti,sysc-omap2ti,syscKPKPKP\revsyscsyssf |fck+ UKPaes@0 ti,omap4-aes U}o}ntxrxtarget-module@4b701000ti,sysc-omap2ti,syscKpKpKp\revsyscsyssf |fck+ UKpaes@0 ti,omap4-aes @}r}qtxrxtarget-module@4b100000ti,sysc-omap3-shamti,syscKKK\revsyscsyss f |(fck+ UKsham@0ti,omap4-sham 3}wrxregulator-abb-mpu ti,abb-v2abb_mpu+-2>{okayJ0{J0`J"h'\base-addressint-addressefuse-addressxNO1regulator-abb-iva ti,abb-v2abb_iva+-2>{okayJ0{J0`J"h'\base-addressint-addressefuse-addressxN~e  target-module@56000000ti,sysc-omap4ti,syscVV \revsyscwf fck+ UVtarget-module@58000000ti,sysc-omap2ti,syscXX \revsyss0 fckhdmi_clksys_clktv_clk+ UXdss@0 ti,omap4-dss{okay fck+ Udefaulttarget-module@1000ti,sysc-omap2ti,sysc\revsyscsyss f w  fcksys_clk+ Udispc@0ti,omap4-dispc  fcktarget-module@2000ti,sysc-omap2ti,sysc   \revsyscsyss f  fcksys_clk+ U encoder@0 {disabledLfckicktarget-module@3000ti,sysc-omap2ti,sysc0\rev sys_clk+ U0encoder@0ti,omap4-venc {disabled fcktarget-module@4000ti,sysc-omap2ti,sysc@@@\revsyscsyss f+ U@encoder@0 ti,omap4-dsi@ \protophypll 5 {disabled  fcksys_clktarget-module@5000ti,sysc-omap2ti,syscPPP\revsyscsyss f+ UPencoder@0 ti,omap4-dsi@ \protophypll T{okay  fcksys_clkZtarget-module@6000ti,sysc-omap4ti,sysc`` \revsyscf  fckdss_clk+ U` encoder@0ti,omap4-hdmi \wppllphycore e{okay  fcksys_clk}L audio_txdefaulteportendpointqportendpointqbandgap@4a002260J"`J#,J#xti,omap4460-bandgap ~ Kthermal-zonescpu_thermal\۫tripscpu_alertpassivecpu_critH criticalcooling-mapsmap0 memory@80000000memory@soundti,abe-twl6040 VAR-SOM-OM44I$-L8Headset StereophoneHSOLHeadset StereophoneHSORAFMLLine InAFMRLine Inhsusb1_phyusb-nop-xceivdefault IyUQ/ main_clk$`fixedregulator-vbatregulator-fixedVBAT2Z2Z`wl12xx_vmmcdefaultregulator-fixedvwl1271w@w@ \ rpxleds gpio-ledsdefaultled0var:green:led0 Ky  heartbeatled1var:green:led1 Ky gpio-keys gpio-keysdefault+user-key@184user Kyconnectorhdmi-connectordefaulthdmia portendpointqdisplayinnolux,at070tn83panel-dpilcdpanel-timingU( (0   portendpointqbacklightgpio-backlightdefault Kq compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3serial0serial1serial2serial3rproc0rproc1display0display1device_typenext-level-cacheregclocksclock-namesclock-latencyoperating-points#cooling-cellsphandleti,hwmodsinterruptsinterrupt-controller#interrupt-cellscache-unifiedcache-levelsramrangesreg-namesti,sysc-sidle#clock-cellsti,index-starts-at-oneti,bit-shiftclock-multclock-divti,max-divti,dividers#reset-cellsti,sysc-maskti,syss-maskti,gpio-always-ongpio-controller#gpio-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsstatus#pinctrl-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinsclock-frequencyti,autoidle-shiftti,invert-autoidle-bitti,index-power-of-twoassigned-clock-ratesti,clock-divti,clock-multti,sysc-midle#dma-cellsdma-channelsdma-requestsinterrupt-namesport1-moderemote-wakeup-connectedphysresetsreset-names#iommu-cellsusb-phyphy-namesmultipointnum-epsram-bitsctrl-moduleinterface-typepower#phy-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rx#hwlock-cellssysconregulator-nameregulator-min-microvoltregulator-max-microvoltti,sysc-delay-usti,timer-pwmregulator-always-onusb-supply#pwm-cells#io-channel-cellsti,audpwron-gpiovio-supplyv2v1-supplyenable-active-highti,buffer-sizedmasdma-namesti,spi-num-csspi-max-frequencyti,dual-voltti,needs-special-resetpbias-supplyvmmc-supplybus-widthti,non-removablecap-power-off-cardref-clock-frequencycd-gpiosti,timer-dspgpmc,num-csgpmc,num-waitpinsti,no-idle-on-initti,iommu-bus-err-backphy-typehw-caps-read-idle-ctrlhw-caps-ll-interfacehw-caps-temp-alertti,bootregiommusfirmware-namemboxesti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infovdd-supplyvdda-supplyremote-endpointdata-lines#thermal-sensor-cellspolling-delay-passivepolling-delaythermal-sensorscoefficientstemperaturehysteresistripcooling-deviceti,modelti,mclk-freqti,mcpdmti,twl6040ti,audio-routingreset-gpiosvcc-supplyregulator-boot-onstartup-delay-uslabellinux,default-triggerlinux,codewakeup-sourcehpd-gpioshback-porchhactivehfront-porchhsync-lenvback-porchvactivevfront-porchvsync-len