\8V|(VD',mundoreader,bq-curie2rockchip,rk3066a 7bq Curie 2aliases=/ethernet@10204000G/i2c@2002d000L/i2c@2002f000Q/i2c@20056000V/i2c@2005a000[/i2c@2005e000`/mmc@1021c000f/mmc@10214000l/mmc@10218000r/serial@10124000z/serial@10126000/serial@20064000/serial@20068000/spi@20070000/spi@20074000bus ,simple-busdma-controller@20018000,arm,pl330arm,primecell @ apb_pclkdma-controller@2001c000,arm,pl330arm,primecell @ apb_pclk  disableddma-controller@20078000,arm,pl330arm,primecell @ apb_pclk oscillator ,fixed-clockn6!.xin24mgpu@10090000",rockchip,rk3066-maliarm,mali-400  buscoreAQfx  disabledx5mgpgpmmupp0ppmmu0pp1ppmmu1pp2ppmmu2pp3ppmmu3}cache-controller@10138000,arm,pl310-cache0scu@1013c000,arm,cortex-a9-scuglobal-timer@1013c200,arm,cortex-a9-global-timer   local-timer@1013c600,arm,cortex-a9-twd-timer   interrupt-controller@1013d000,arm,cortex-a9-gicserial@10124000&,rockchip,rk3066-uartsnps,dw-apb-uart@ "baudclkapb_pclk@L okaytxrxdefaultserial@10126000&,rockchip,rk3066-uartsnps,dw-apb-uart` #baudclkapb_pclkAM okaytxrxdefaultqos@1012d000,syscon qos@1012e000,syscon qos@1012f000,syscon qos@1012f080,syscon qos@1012f100,syscon qos@1012f180,syscon qos@1012f200,syscon qos@1012f280,syscon usb@10180000,rockchip,rk3066-usbsnps,dwc2 otg otg#2@@ A Fusb2-phy  disabledusb@101c0000 ,snps,dwc2 otg hostA Fusb2-phy  disabledethernet@10204000,rockchip,rk3066-emac @< P D hclkmacref]dgrmii  disabledmmc@10214000,rockchip,rk2928-dw-mshc!@ Hbiuciu rx-txpfQ{reset okaydefault mmc@10218000,rockchip,rk2928-dw-mshc! Ibiuciu rx-txpfR{reset okaydefault mmc@1021c000,rockchip,rk2928-dw-mshc! Jbiuciu rx-txpfS{reset  disabledpmu@20004000&,rockchip,rk3066-pmusysconsimple-mfd @reboot-mode,syscon-reboot-mode@RBRBRB RBpower-controller!,rockchip,rk3066-power-controller$pd_vio@7PO8pd_video@6 8pd_gpu@88grf@20008000,syscon  i2c@2002d000,rockchip,rk3066-i2c  (P i2cP  disableddefaulti2c@2002f000,rockchip,rk3066-i2c  )P Qi2c okaydefaulttps@2d-?K ,ti,tps65910regulatorsregulator@0Wvcc_rtcfzvrtcregulator@1Wvcc_iofzvioregulator@2Wvdd_arm '`fzvdd11regulator@3Wvcc_ddr '`fzvdd2regulator@5 Wvcc18_ciffzvdig1regulator@6Wvdd_11fzvdig2regulator@7Wvcc_25fzvpllregulator@8Wvcc_18fzvdacregulator@9 Wvcc25_hdmif zvaux1regulator@10Wvcca_33f zvaux2regulator@11Wvcc_tpf zvaux33regulator@12 Wvcc28_ciff zvmmcregulator@4zvdd3regulator@13 zvbbpwm@20030000,rockchip,rk2928-pwm F  disableddefaultpwm@20030010,rockchip,rk2928-pwm F  disableddefault watchdog@2004c000 ,rockchip,rk3066-wdtsnps,dw-wdt K 3 okaypwm@20050020,rockchip,rk2928-pwm  G  disableddefault!pwm@20050030,rockchip,rk2928-pwm 0G okaydefault"?i2c@20056000,rockchip,rk3066-i2c ` *P Ri2c  disableddefault#i2c@2005a000,rockchip,rk3066-i2c  +P Si2c  disableddefault$i2c@2005e000,rockchip,rk3066-i2c  4P Ti2c  disableddefault%serial@20064000&,rockchip,rk3066-uartsnps,dw-apb-uart @ $baudclkapb_pclkBN okay  txrxdefault&serial@20068000&,rockchip,rk3066-uartsnps,dw-apb-uart  %baudclkapb_pclkCO okay  txrxdefault'saradc@2006c000,rockchip,saradc  GJsaradcapb_pclkfW {saradc-apb  disabledspi@20070000,rockchip,rk3066-spiEHspiclkapb_pclk &  txrx  disableddefault()*+spi@20074000,rockchip,rk3066-spiFIspiclkapb_pclk ' @ txrx  disableddefault,-./cpusrockchip,rk3066-smpcpu@0cpu,arm,cortex-a908@ Oa* s* 'g8*@81cpu@1cpu,arm,cortex-a90display-subsystem,rockchip,display-subsystemD23sram@10080000 ,mmio-sram smp-sram@0,rockchip,rk3066-smp-sramPvop@1010c000,rockchip,rk3066-vop aclk_vopdclk_vophclk_vop}fdef {axiahbdclk  disabledport2endpoint@0J48vop@1010e000,rockchip,rk3066-vop aclk_vopdclk_vophclk_vop}fghi {axiahbdclk  disabledport3endpoint@0J59hdmi@10116000,rockchip,rk3066-hdmi`  @hclkdefault67}P   disabledportsport@0endpoint@0J84endpoint@1J95port@1i2s@10118000,rockchip,rk3066-i2s  default:Ki2s_clki2s_hclktxrxZu  disabledi2s@1011a000,rockchip,rk3066-i2s  default;Li2s_clki2s_hclktxrxZu  disabledi2s@1011c000,rockchip,rk3066-i2s  default<Mi2s_clki2s_hclk  txrxZu  disabledclock-controller@20000000,rockchip,rk3066a-cru P !@A^_ Qׄ#gрxhрxhtimer@2000e000,snps,dw-apb-timer-osc  .VD timerpclkefuse@20010000,rockchip,rk3066a-efuse @[ pclk_efusecpu_leakage@17timer@20038000,snps,dw-apb-timer-osc  ,TB timerpclktimer@2003a000,snps,dw-apb-timer-osc  -UC timerpclktsadc@20060000,rockchip,rk3066-tsadc ]]saradcapb_pclk f\ {saradc-apb  disabledphy1,rockchip,rk3066a-usb-phyrockchip,rk3288-usb-phyP   disabledusb-phy@17c|Qphyclk!usb-phy@188Rphyclk!pinctrl,rockchip,rk3066a-pinctrlP gpio0@20034000,rockchip,gpio-bank @ 6Ugpio1@2003c000,rockchip,gpio-bank  7Vgpio2@2003e000,rockchip,gpio-bank  8Wgpio3@20080000,rockchip,gpio-bank  9X@gpio4@20084000,rockchip,gpio-bank @ :YAgpio6@2000a000,rockchip,gpio-bank  <Zpcfg_pull_default>pcfg_pull_none=emacemac-xfer========emac-mdio ==emmcemmc-clk>emmc-cmd >emmc-rst >hdmihdmi-hpd>7hdmii2c-xfer ==6i2c0i2c0-xfer ==i2c1i2c1-xfer ==i2c2i2c2-xfer ==#i2c3i2c3-xfer ==$i2c4i2c4-xfer ==%pwm0pwm0-out=pwm1pwm1-out= pwm2pwm2-out=!pwm3pwm3-out="spi0spi0-clk>(spi0-cs0>+spi0-tx>)spi0-rx>*spi0-cs1>spi1spi1-clk>,spi1-cs0>/spi1-rx>.spi1-tx>-spi1-cs1>uart0uart0-xfer >>uart0-cts>uart0-rts>uart1uart1-xfer >>uart1-cts>uart1-rts>uart2uart2-xfer > >&uart3uart3-xfer >>'uart3-cts>uart3-rts>sd0sd0-clk> sd0-cmd > sd0-cd> sd0-wp>sd0-bus-width1 >sd0-bus-width4@ > > > >sd1sd1-clk>sd1-cmd>sd1-cd>sd1-wp>sd1-bus-width1>sd1-bus-width4@>>>>i2s0i2s0-bus>> > > > > >>>:i2s1i2s1-bus`>>>>>>;i2s2i2s2-bus`>>>>>><memory@60000000memory`@vdd-log,pwm-regulator ?Wvdd_logOOf B@dO* okayfixed-regulator,regulator-fixed Wsdmmc-supply-- @.gpio-keys ,gpio-keys9power DJtUGPIO Key Power[lzdvolume-down DAJrUGPIO Key Vol-[zd #address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4mshc0mshc1mshc2serial0serial1serial2serial3spi0spi1rangesreginterrupts#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstclocksclock-namesphandlestatusclock-frequency#clock-cellsclock-output-namesassigned-clocksassigned-clock-ratesresetsinterrupt-namespower-domainscache-unifiedcache-levelinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthdmasdma-namespinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesrockchip,grfmax-speedphy-modefifo-depthreset-namesmax-frequencyvmmc-supplybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpnon-removableoffsetmode-normalmode-recoverymode-bootloadermode-loader#power-domain-cellspm_qosvcc5-supplyvcc6-supplyregulator-nameregulator-always-onregulator-compatibleregulator-min-microvoltregulator-max-microvoltregulator-boot-on#pwm-cells#io-channel-cellsenable-methoddevice_typenext-level-cacheoperating-pointsclock-latencycpu0-supplyportsremote-endpointrockchip,playback-channelsrockchip,capture-channels#sound-dai-cells#reset-cells#phy-cellsgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinspwmsvoltage-tablegpiostartup-delay-usvin-supplyautorepeatgpioslinux,codelabellinux,input-typewakeup-sourcedebounce-interval