8$(mqmaker,miqirockchip,rk3288& 7mqmaker MiQialiases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/mmc@ff0f0000k/mmc@ff0c0000q/mmc@ff0d0000w/mmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12'@5<rV bcpu@501cpuarm,cortex-a12'@5<rbcpu@502cpuarm,cortex-a12'@5<rbcpu@503cpuarm,cortex-a12'@5<rbcpu-opp-tableoperating-points-v2jbopp-126000000u| opp-216000000u | opp-312000000u| opp-408000000uQ| opp-600000000u#F| opp-696000000u)||~opp-816000000u0,|B@opp-1008000000u<|opp-1200000000uG|opp-1416000000uTfr|Oopp-1512000000uZJ| opp-1608000000u_"|pbus simple-busdma-controller@ff250000arm,pl330arm,primecell%@5 apb_pclkbdma-controller@ff600000arm,pl330arm,primecell`@5 apb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@5 apb_pclkbZreserved-memorydma-unusable@fe000000oscillator fixed-clockn6xin24mb timerarm,armv7-timer0   n65timer@ff810000rockchip,rk3288-timer  H 5 a timerpclkdisplay-subsystemrockchip,display-subsystemL mmc@ff0c0000rockchip,rk3288-dw-mshcRр 5Drvbiuciuciu-driveciu-sample`  @kresetokaywdefault mmc@ff0d0000rockchip,rk3288-dw-mshcRр 5Eswbiuciuciu-driveciu-sample` ! @kreset disabledmmc@ff0e0000rockchip,rk3288-dw-mshcRр 5Ftxbiuciuciu-driveciu-sample` "@kreset disabledmmc@ff0f0000rockchip,rk3288-dw-mshcRр 5Guybiuciuciu-driveciu-sample` #@kresetokaywdefaultsaradc@ff100000rockchip,saradc $5I[saradcapb_pclkW ksaradc-apbokayspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi5ARspiclkapb_pclk  #txrx ,default disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi5BSspiclkapb_pclk #txrx -default !" disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi5CTspiclkapb_pclk#txrx .default#$%& disabledi2c@ff140000rockchip,rk3288-i2c >i2c5Mdefault'okayi2c@ff150000rockchip,rk3288-i2c ?i2c5Odefault( disabledi2c@ff160000rockchip,rk3288-i2c @i2c5Pdefault)okayi2c@ff170000rockchip,rk3288-i2c Ai2c5Qdefault*okaybpserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 7-75MUbaudclkapb_pclk#txrxdefault+ disabledserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 8-75NVbaudclkapb_pclk#txrxdefault, disabledserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 9-75OWbaudclkapb_pclkdefault-okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :-75PXbaudclkapb_pclk#txrxdefault.okayserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;-75QYbaudclkapb_pclk  #txrxdefault/ disabledthermal-zonesreserve_thermalDZh0cpu_thermalDdZh0tripscpu_alert0xppassiveb1cpu_alert1x$passiveb2cpu_critx_ criticalcooling-mapsmap010map120gpu_thermalDdZh0tripsgpu_alert0xppassiveb3gpu_critx_ criticalcooling-mapsmap03 4tsadc@ff280000rockchip,rk3288-tsadc( %5HZtsadcapb_pclk ktsadc-apbinitdefaultsleep5657sokayb0ethernet@ff290000rockchip,rk3288-gmac)#macirqeth_wake_irq785fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB kstmmacethok3C8Zinputdefault9:;<g=rrgmii{ 'B@ >0usb@ff500000 generic-ehciP 5?usb disabledusb@ff520000 generic-ohciR )5?usb disabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 5otghost@ usb2-phyokayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 5otg peripheral@@ A usb2-phyokayusb@ff5c0000 generic-ehci\ 5 disabledi2c@ff650000rockchip,rk3288-i2ce <i2c5LdefaultBokaysyr827@40silergy,syr827&@Cvdd_cpuR Pjp,@Cb syr828@41silergy,syr828&ACvdd_gpuR PjpChym8563@51haoyu,hym8563Qxin32kact8846@5aactive-semi,act8846ZdefaultDCCCC(C4C@EregulatorsREG1Cvcc_ddrREG2Cvcc_ioR2Zj2ZbREG3Cvdd_logRjREG4Cvcc_20RjbEREG5 Cvccio_sdR2Zj2ZbREG6 Cvdd10_lcdRB@jB@REG7Cvcca_18Rw@jw@REG8Cvcca_33R2Zj2ZbYREG9Cvcc_lanR2Zj2Zb=REG10Cvdd_10RB@jB@REG11Cvcc_18Rw@jw@bREG12 Cvcc18_lcdRw@jw@i2c@ff660000rockchip,rk3288-i2cf =i2c5NdefaultFokaypwm@ff680000rockchip,rk3288-pwmhLdefaultG5_pwm disabledpwm@ff680010rockchip,rk3288-pwmhLdefaultH5_pwm disabledpwm@ff680020rockchip,rk3288-pwmh LdefaultI5_pwm disabledpwm@ff680030rockchip,rk3288-pwmh0LdefaultJ5_pwm disabledsram@ff700000 mmio-sramppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsbpower-controller!rockchip,rk3288-power-controllerW3hC b]pd_vio@9 5chgfdehilkj$kKLMNOPQRSpd_hevc@11 5opkTUpd_video@12 5kVpd_gpu@13 5kWXreboot-modesyscon-reboot-moderyRBRBRB RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv7H3jk$#gׄeрxhрxhbsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwb7edp-phyrockchip,rk3288-dp-phy5h24m disabledbmio-domains"rockchip,rk3288-io-voltage-domainokayY=#/=usbphyrockchip,rk3288-usb-phyokayusb-phy@320 5]phyclk kphy-resetbAusb-phy@33445^phyclk kphy-resetb?usb-phy@348H5_phyclk kphy-resetb@watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt5p Ookaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdifI5T mclkhclkZ#tx 6default[7 disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2sI 55Ri2s_clki2s_hclkZZ#txrxdefault\Zu disabledcypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 5}aclkhclksclkapb_pclk kcrypto-rstokayiommu@ff900800rockchip,iommu@ #iep_mmu5 aclkiface disablediommu@ff914000rockchip,iommu @P #isp_mmu5 aclkiface disabledrga@ff920000rockchip,rk3288-rga 5jaclkhclksclk] ilm kcoreaxiahbvop@ff930000rockchip,rk3288-vop  5aclk_vopdclk_vophclk_vop] def kaxiahbdclk^okayportb endpoint@0_bqendpoint@1`bnendpoint@2abhendpoint@3bbkiommu@ff930300rockchip,iommu  #vopb_mmu5 aclkiface] okayb^vop@ff940000rockchip,rk3288-vop  5aclk_vopdclk_vophclk_vop]  kaxiahbdclkcokayportb endpoint@0dbrendpoint@1eboendpoint@2fbiendpoint@3gbliommu@ff940300rockchip,iommu  #vopl_mmu5 aclkiface] okaybcmipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ 5~d refpclk] 7 disabledportsportendpoint@0hbaendpoint@1ibflvds@ff96c000rockchip,rk3288-lvds@5g pclk_lvdslcdcj] 7 disabledportsport@0endpoint@0kbbendpoint@1lbgdp@ff970000rockchip,rk3288-dp@ b5icdppclkmdpokdp7 disabledportsport@0endpoint@0nb`endpoint@1obehdmi@ff980000rockchip,rk3288-dw-hdmi7I7 g5hmniahbisfrcec] okaypportsportendpoint@0qb_endpoint@1rbdvideo-codec@ff9a0000rockchip,rk3288-vpu   #vepuvdpu5 aclkhclks] iommu@ff9a0800rockchip,iommu #vpu_mmu5 aclkiface] bsiommu@ff9c0440rockchip,iommu @@@ o #hevc_mmu5 aclkiface disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ #jobmmugpu5t]  disabledb4gpu-opp-tableoperating-points-v2btopp-100000000u|~opp-200000000u |~opp-300000000u|B@opp-400000000uׄ|opp-600000000u#F|qos@ffaa0000syscon bWqos@ffaa0080syscon bXqos@ffad0000syscon bLqos@ffad0100syscon bMqos@ffad0180syscon bNqos@ffad0400syscon bOqos@ffad0480syscon bPqos@ffad0500syscon bKqos@ffad0800syscon bQqos@ffad0880syscon bRqos@ffad0900syscon bSqos@ffae0000syscon bVqos@ffaf0000syscon bTqos@ffaf0080syscon bUefuse@ffb40000rockchip,rk3288-efuse 5q pclk_efusecpu-id@7cpu_leakage@17interrupt-controller@ffc01000 arm,gic-400@ @ `   bpinctrlrockchip,rk3288-pinctrl7gpio0@ff750000rockchip,gpio-banku Q5@b}gpio1@ff780000rockchip,gpio-bankx R5Agpio2@ff790000rockchip,gpio-banky S5Bgpio3@ff7a0000rockchip,gpio-bankz T5Cgpio4@ff7b0000rockchip,gpio-bank{ U5Db>gpio5@ff7c0000rockchip,gpio-bank| V5Egpio6@ff7d0000rockchip,gpio-bank} W5Fgpio7@ff7e0000rockchip,gpio-bank~ X5Gb|gpio8@ff7f0000rockchip,gpio-bank Y5Hhdmihdmi-cec-c0*uhdmi-cec-c7*uhdmi-ddc *uuhdmi-ddc-unwedge *vupcfg-output-low8bvpcfg-pull-upCbwpcfg-pull-downPbxpcfg-pull-none_bupcfg-pull-none-12ma_l bysleepglobal-pwroff*uddrio-pwroff*uddr0-retention*wddr1-retention*wedpedp-hpd* xi2c0i2c0-xfer *uubBi2c1i2c1-xfer *uub'i2c2i2c2-xfer * u ubFi2c3i2c3-xfer *uub(i2c4i2c4-xfer *uub)i2c5i2c5-xfer *uub*i2s0i2s0-bus`*uuuuuub\lcdclcdc-ctl@*uuuubjsdmmcsdmmc-clk*yb sdmmc-cmd*zbsdmmc-cd*wbsdmmc-bus1*wsdmmc-bus4@*zzzzbsdmmc-pwr* ubsdio0sdio0-bus1*wsdio0-bus4@*wwwwsdio0-cmd*wsdio0-clk*usdio0-cd*wsdio0-wp*wsdio0-pwr*wsdio0-bkpwr*wsdio0-int*wsdio1sdio1-bus1*wsdio1-bus4@*wwwwsdio1-cd*wsdio1-wp*wsdio1-bkpwr*wsdio1-int*wsdio1-cmd*wsdio1-clk*usdio1-pwr* wemmcemmc-clk*ubemmc-cmd*wbemmc-pwr* wbemmc-bus1*wemmc-bus4@*wwwwemmc-bus8*wwwwwwwwbspi0spi0-clk* wbspi0-cs0* wbspi0-tx*wbspi0-rx*wbspi0-cs1*wspi1spi1-clk* wbspi1-cs0* wb"spi1-rx*wb!spi1-tx*wb spi2spi2-cs1*wspi2-clk*wb#spi2-cs0*wb&spi2-rx*wb%spi2-tx* wb$uart0uart0-xfer *wub+uart0-cts*wuart0-rts*uuart1uart1-xfer *w ub,uart1-cts* wuart1-rts* uuart2uart2-xfer *wub-uart3uart3-xfer *wub.uart3-cts* wuart3-rts* uuart4uart4-xfer *wub/uart4-cts* wuart4-rts* utsadcotp-pin* ub5otp-out* ub6pwm0pwm0-pin*ubGpwm1pwm1-pin*ubHpwm2pwm2-pin*ubIpwm3pwm3-pin*ubJgmacrgmii-pins*uuuuyyyyuuu yyuub9rmii-pins*uuuuuuuuuuphy-int* wb<phy-pmeb*wb;phy-rst*{b:spdifspdif-tx* ub[pcfg-output-high{b{pcfg-pull-up-drv-12maCl bzact8846pmic-int*wpmic-sleep*vpmic-vsel*vbDusb_hosthost-vbus-drv*ub~chosenserial2:115200n8memory@0memoryexternal-gmac-clock fixed-clocksY@ ext_gmacb8leds gpio-ledsled-0 |miqi:green:usertimerflash-regulatorregulator-fixed Cvcc_flashRw@jw@busb-host-regulatorregulator-fixed }default~ Cvcc_hostRLK@jLK@Csdmmc-regulatorregulator-fixed | defaultCvcc_sdR2Zj2Zbvsys-regulatorregulator-fixedCvcc_sysRLK@jLK@bC #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltranges#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendportsmax-frequencyfifo-depthreset-namesbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wppinctrl-namespinctrl-0vmmc-supplyvqmmc-supplynon-removable#io-channel-cellsvref-supplydmasdma-namesreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-active-lowsnps,reset-delays-ussnps,reset-gpiotx_delayrx_delayphysphy-namesdr_modesnps,reset-phy-on-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizefcs,suspend-voltage-selectorregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-enable-ramp-delayregulator-ramp-delayvin-supplysystem-power-controllervp1-supplyvp2-supplyvp3-supplyvp4-supplyinl1-supplyinl2-supplyinl3-supply#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsaudio-supplyflash0-supplyflash1-supplygpio30-supplygpio1830-supplylcdc-supplysdcard-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointddc-i2c-businterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathgpioslabellinux,default-triggerenable-active-highstartup-delay-us