3N8/(j/.STMicroelectronics STM32H743i-Discovery board!!st,stm32h743i-discost,stm32h743interrupt-controller@e000e100!arm,armv7m-nvic,AR Vtimer@e000e010!arm,armv7m-systickR^okaye沀soc !simple-busutimer@40000c00!st,stm32-timerR@ 2_timer@40002400!st,stm32-lptimerR@$mux ^disabledpwm!st,stm32-pwm-lp ^disabledtrigger@0!st,stm32-lptimer-triggerR ^disabledcounter!st,stm32-lptimer-counter ^disabledspi@40003800!st,stm32h7-spiR@8$ ^disabledspi@40003c00!st,stm32h7-spiR@<3 ^disabledserial@40004400!st,stm32f7-uartR@D&^okaydefaulti2c@40005400!st,stm32f7-i2cR@T  ^disabledi2c@40005800!st,stm32f7-i2cR@X!" ^disabledi2c@40005C00!st,stm32f7-i2cR@\HI ^disableddac@40007400!st,stm32h7-dac-coreR@tXpclk ^disableddac@1 !st,stm32-dacR ^disableddac@2 !st,stm32-dacR ^disabledserial@40011000!st,stm32f7-uartR@% ^disabledspi@40013000!st,stm32h7-spiR@0# ^disabledspi@40013400!st,stm32h7-spiR@4T ^disabledspi@40015000!st,stm32h7-spiR@PU ^disableddma-controller@40020000 !st,stm32-dmaR@ /A ^disabledVdma-controller@40020400 !st,stm32-dmaR@ 89:;<DEF@ ^disabledVdma-router@40020800!st,stm32h7-dmamuxR@ Aadc@40022000!st,stm32h7-adc-coreR@ }bus,A ^disabledVadc@0!st,stm32h7-adcRu ^disabledadc@100!st,stm32h7-adcRu ^disabledusb@40040000!st,stm32f7-hsotgR@M|otg#2  D@@@@  ^disabledusb@40080000!st,stm32f4x9-fsotgR@e{otg ^disableddma-controller@52000000!st,stm32h7-mdmaRRz9  sdmmc@52007000!arm,pl18xarm,primecellS1RRp1jcmd_irqx apb_pclkz'defaultopendrainsleep  ^okayinterrupt-controller@58000000!st,stm32h7-exti,ARX4 ()>LV syscon@58000400!st,stm32-syscfgsysconRXVspi@58001400!st,stm32h7-spiRXV ^disabledi2c@58001C00!st,stm32f7-i2cRX_` ^disabledtimer@58002400!st,stm32-lptimerRX$mux ^disabledpwm!st,stm32-pwm-lp ^disabledtrigger@1!st,stm32-lptimer-triggerR ^disabledcounter!st,stm32-lptimer-counter ^disabledtimer@58002800!st,stm32-lptimerRX(mux ^disabledpwm!st,stm32-pwm-lp ^disabledtrigger@2!st,stm32-lptimer-triggerR ^disabledtimer@58002c00!st,stm32-lptimerRX,mux ^disabledpwm!st,stm32-pwm-lp ^disabledtimer@58003000!st,stm32-lptimerRX0mux ^disabledpwm!st,stm32-pwm-lp ^disabledregulator@58003c00!st,stm32-vrefbufRX<m`&% ^disabledrtc@58004000!st,stm32h7-rtcRX@l  pclkrtc_ck + u  B  ^disabledreset-clock-controller@58024400!st,stm32h743-rccst,stm32-rccRXDLY B Vpower-config@58024800!st,stm32-power-configsysconRXHV adc@58026000!st,stm32h7-adc-coreRX`bus,A ^disabledVadc@0!st,stm32h7-adcRu ^disabledethernet@40028000 !st,stm32-dwmacsnps,dwmac-4.10aR@ fstmmaceth=jmacirq stmmacethmac-clk-txmac-clk-rx>=<pz ^disableddefaultrmiimdio0!snps,dwmac-mdioethernet-phy@0RVpin-controller!st,stm32h743-pinctrl X0u Bgpio@58020000RVGPIOA,Agpio@58020400RUGPIOB,Agpio@58020800RTGPIOC,Agpio@58020c00R SGPIOD,Agpio@58021000RRGPIOE,Agpio@58021400RQGPIOF,Agpio@58021800RPGPIOG,Agpio@58021c00ROGPIOH,Agpio@58022000R NGPIOI,Agpio@58022400R$MGPIOJ,Agpio@58022800R(LGPIOK,Ai2c1-0pinsrmii-0Vpins$k m l $ %  !   sdmmc1-b4-0Vpins( ) * + , 2 sdmmc1-b4-od-0Vpins1( ) * + , pins22 sdmmc1-b4-sleep-0V pins()*+,2sdmmc1-dir-0pins1 & ' pins2sdmmc1-dir-sleep-0pins&'usart1-0pins1pins2usart2-0Vpins15pins26usbotg-hs-0pins0t          clocksclk-hseL !fixed-clocke}x@V clk-lseL !fixed-clockeVi2s_ckinL !fixed-clockeVchosenroot=/dev/ram'serial0:115200n8memory@d00000003memoryRaliases?/soc/serial@40004400regulator-v3v3!regulator-fixedGv3v32Z2ZVV  #address-cells#size-cellsmodelcompatibleinterrupt-controller#interrupt-cellsregphandlestatusclock-frequencyinterrupt-parentrangesinterruptsclocksclock-names#pwm-cellspinctrl-0pinctrl-namesresets#io-channel-cells#dma-cellsst,mem2memdma-requestsdma-channelsdma-mastersg-rx-fifo-sizeg-np-tx-fifo-sizeg-tx-fifo-sizearm,primecell-periphidinterrupt-namescap-sd-highspeedcap-mmc-highspeedmax-frequencypinctrl-1pinctrl-2broken-cdst,neg-edgebus-widthvmmc-supplyregulator-min-microvoltregulator-max-microvoltassigned-clocksassigned-clock-parentsst,syscfg#clock-cells#reset-cellsreg-namesst,sysconsnps,pblphy-modephy-handlepins-are-numberedgpio-controller#gpio-cellsst,bank-namepinmuxbias-disabledrive-open-drainslew-ratedrive-push-pullbias-pull-upbootargsstdout-pathdevice_typeserial0regulator-nameregulator-always-on