)N8&\(&$ ,NXP i.MX8ULP EVK2fsl,imx8ulp-evkfsl,imx8ulpaliases&=/soc@0/bus@29800000/ethernet@29950000G/soc@0/gpio@2e200080M/soc@0/gpio@2d000080S/soc@0/gpio@2d010080!Y/soc@0/bus@29800000/mmc@298d0000!^/soc@0/bus@29800000/mmc@298e0000!c/soc@0/bus@29800000/mmc@298f0000$h/soc@0/bus@29000000/serial@29390000$p/soc@0/bus@29000000/serial@293a0000$x/soc@0/bus@29800000/serial@29860000$/soc@0/bus@29800000/serial@29870000cpus cpu@0cpu2arm,cortex-a35pscicpu@1cpu2arm,cortex-a35pscil2-cache02cacheinterrupt-controller@2d400000 2arm,gic-v3 -@-D   pmu2arm,cortex-a35-pmu psci 2arm,psci-1.0smctimer2arm,armv8-timer0   clock-frosc 2fixed-clock qfrosc&clock-lposc 2fixed-clockB@lposc&clock-rosc 2fixed-clockrosc&clock-sosc 2fixed-clockn6sosc&sram@2201f000 2mmio-sram" 3"scmi-sram-section@02arm,scmi-shmemfirmwarescmi 2arm,scmi-smc: Eprotocol@11K protocol@15_soc@0 2simple-bus 3@mailbox@270200002fsl,imx8ulp-mu-s4' Oubus@29000000 2simple-bus) 3mailbox@292200002fsl,imx8ulp-mu)" Iu disabledmailbox@292300002fsl,imx8ulp-mu)# K.u disabledwatchdog@292a0000 2fsl,imx8ulp-wdtfsl,imx7ulp-wdt)* L(clock-controller@292c00002fsl,imx8ulp-cgc1),&clock-controller@292d00002fsl,imx8ulp-pcc3)-&tpm@29340000 2fsl,imx8ulp-tpmfsl,imx7ulp-tpm)4 Wipgper disabledi2c@29370000$2fsl,imx8ulp-lpi2cfsl,imx7ulp-lpi2c)7 \peripg"l disabledi2c@29380000$2fsl,imx8ulp-lpi2cfsl,imx7ulp-lpi2c)8 ]peripg"l disabledserial@29390000&2fsl,imx8ulp-lpuartfsl,imx7ulp-lpuart)9 c ipg disabledserial@293a0000&2fsl,imx8ulp-lpuartfsl,imx7ulp-lpuart): d ipgokaydefaultsleepspi@293b0000  2fsl,imx8ulp-spifsl,imx7ulp-spi); a  peripg "l disabledspi@293c0000  2fsl,imx8ulp-spifsl,imx7ulp-spi)< b  peripg "l disabledbus@29800000 2simple-bus) 3clock-controller@298000002fsl,imx8ulp-pcc4)& i2c@29840000$2fsl,imx8ulp-lpi2cfsl,imx7ulp-lpi2c) ^  peripg "l disabledi2c@29850000$2fsl,imx8ulp-lpi2cfsl,imx7ulp-lpi2c) _  peripg "l disabledserial@29860000&2fsl,imx8ulp-lpuartfsl,imx7ulp-lpuart) e ipg disabledserial@29870000&2fsl,imx8ulp-lpuartfsl,imx7ulp-lpuart) f ipg disabledpinctrl@298c00002fsl,imx8ulp-iomuxc1)enetgrp C C  C C C C C C C C( C lpuart5grp(8<usdhc0grpCB(C$C CCCCC C,B mmc@298d0000#2fsl,imx8ulp-usdhcfsl,imx8mm-usdhc)   ipgahbper )>Nokaydefaultsleep  Xmmc@298e0000#2fsl,imx8ulp-usdhcfsl,imx8mm-usdhc)   ipgahbper )>N disabledmmc@298f0000#2fsl,imx8ulp-usdhcfsl,imx8mm-usdhc)   ipgahbper )>N disabledethernet@29950000-2fsl,imx8ulp-fecfsl,imx6ul-fecfsl,imx6q-fec) kfint0vokaydefaultsleep   7 ipgahbptpenet_clk_ref7rmiimdio ethernet-phy@1gpio@2d000080"2fsl,imx8ulp-gpiofsl,imx7ulp-gpio--@@    gpioport gpio@2d010080"2fsl,imx8ulp-gpiofsl,imx7ulp-gpio--@@    gpioport@ bus@2d800000 2simple-bus- 3clock-controller@2da600002fsl,imx8ulp-cgc2-&clock-controller@2da700002fsl,imx8ulp-pcc5-&gpio@2e200080"2fsl,imx8ulp-gpiofsl,imx7ulp-gpio. . @@  gpioportchosen$/soc@0/bus@29000000/serial@293a0000memory@80000000memoryclock-ext-rmii 2fixed-clock ext_rmii_clk& clock-ext-ts 2fixed-clock ext_ts_clk& interrupt-parent#address-cells#size-cellsmodelcompatibleethernet0gpio0gpio1gpio2mmc0mmc1mmc2serial0serial1serial2serial3device_typeregenable-methodnext-level-cachephandle#interrupt-cellsinterrupt-controllerinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsrangesarm,smc-idshmem#power-domain-cells#thermal-sensor-cells#mbox-cellsstatusclocksassigned-clocksassigned-clock-parentstimeout-sec#reset-cellsclock-namesassigned-clock-ratespinctrl-namespinctrl-0pinctrl-1fsl,pinspower-domainsfsl,tuning-start-tapfsl,tuning-stepbus-widthnon-removableinterrupt-namesfsl,num-tx-queuesfsl,num-rx-queuesphy-modephy-handlemicrel,led-modegpio-controller#gpio-cellsgpio-rangesstdout-path