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/soc@0/geniqup@8c0000/spi@890000!/soc@0/geniqup@8c0000/spi@894000$/soc@0/geniqup@ac0000/serial@a90000chosen!serial0:115200n8clocksxo-board 2fixed-clock-:Ið Jxo_board]Wsleep-clk 2fixed-clock:}-]cpus cpu@0ecpu 2qcom,kryo485qupsciƒl2-cache2cacheƒ]l3-cache2cache]cpu@100ecpu 2qcom,kryo485qupsciƒl2-cache2cacheƒ]cpu@200ecpu 2qcom,kryo485qupsciƒl2-cache2cacheƒ]cpu@300ecpu 2qcom,kryo485qupsciƒl2-cache2cacheƒ]cpu@400ecpu 2qcom,kryo485qupsciƒl2-cache2cacheƒ]cpu@500ecpu 2qcom,kryo485qupsciƒl2-cache2cacheƒ]cpu@600ecpu 2qcom,kryo485qupsciƒ l2-cache2cacheƒ] cpu@700ecpu 2qcom,kryo485qupsciƒ l2-cache2cacheƒ] firmwarescm 2qcom,scm”memory@80000000ememoryq€pmu2arm,armv8-pmuv3 ¡psci 2arm,psci-1.0|smcreserved-memory ¬memory@80000000q€`³memory@80700000q€p³memory@80860000 2qcom,cmd-dbq€†³memory@80900000q€ ³] memory@80b00000q€°0³memory@86200000q† P³memory@86700000q†p³memory@86800000q†€³memory@86810000q† ³memory@8681a000q†  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ëÂ0clock-controller@3d900002qcom,sm8250-gpuccqÙŒ"#8€bi_tcxogcc_gpu_gpll0_clk_srcgcc_gpu_gpll0_div_clk_src-”l]Eiommu@3da0000!2qcom,sm8250-smmu-500arm,mmu-500qÚ>Kx¡ ¡¦§¨©ª«¬­ŒE%&€ahbbusifaceôE]Aremoteproc@5c000002qcom,sm8250-slpi-pasqÀ@<ÚG HHHH#wdogfatalreadyhandoverstop-ackŒ€xoôIJJ+load_statelcxlmxºK^LostopŸokay…qcom/sm8250/slpi.mbnglink-edgeÚ  î “lpassremoteproc@83000002qcom,sm8250-cdsp-pasq0@ÚBMMMM#wdogfatalreadyhandoverstop-ackŒ€xoôIJ+load_statecxºN^OostopŸokay…qcom/sm8250/cdsp.mbnglink-edgeÚ  î “lpassinterrupt-controller@b2200002qcom,sm8250-pdcqcom,pdc q "Àð`0™à^^a}?~Ì P;]Gqmp@c3000002qcom,sm8250-aoss-qmpq 0Ú  î -l]Ispmi@c4400002qcom,spmi-pmic-arbPq D ``p @ `Ücorechnlsobsrvrintrcnfg periph_irq ÚG©± ;Ppmic@02qcom,pm8150qcom,spmi-pmicq power-on@8002qcom,pm8916-ponqpwrkey2qcom,pm8941-pwrkey¡¾= ÇÔt Ÿdisabledtemp-alarm@24002qcom,spmi-temp-alarmq$¡$ßPëthermalü]_adc@31002qcom,spmi-adc5q1 ¡1]Pref-gnd@0q$“ref_gndvref-1p25@1q$ “vref_1p25die-temp@6q$ “die_temprtc@60002qcom,pm8941-rtcq` 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interrupt-parent#address-cells#size-cellsmodelcompatiblei2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8i2c9i2c10i2c11i2c12i2c13i2c14i2c15i2c16i2c17i2c18i2c19spi0spi1spi2spi3spi4spi5spi6spi7spi8spi9spi10spi11spi12spi13spi14spi15spi16spi17spi18spi19serial0stdout-path#clock-cellsclock-frequencyclock-output-namesphandledevice_typeregenable-methodnext-level-cache#reset-cellsinterruptsrangesno-mapmemory-regionhwlocksqcom,smeminterrupts-extendedmboxesqcom,local-pidqcom,remote-pidqcom,entry-name#qcom,smem-state-cellsinterrupt-controller#interrupt-cellsdma-ranges#power-domain-cellsclock-namesclocks#mbox-cellsstatuspinctrl-namespinctrl-0physphy-nameslanes-per-directionresetsreset-namespower-domainsfreq-table-hzvcc-supplyvcc-max-microampvccq-supplyvccq-max-microampvccq2-supplyvccq2-max-microampvdda-phy-supplyvdda-max-microampvdda-pll-supplyvdda-pll-max-microamp#phy-cells#hwlock-cells#stream-id-cellsreg-namesiommusoperating-points-v2qcom,gmuopp-hzopp-levelinterrupt-namespower-domain-names#iommu-cells#global-interruptsqcom,smem-statesqcom,smem-state-namesfirmware-namelabelqcom,pdc-rangesqcom,eeqcom,channeldebouncebias-pull-uplinux,codeio-channelsio-channel-names#thermal-sensor-cells#io-channel-cellsqcom,pre-scalinggpio-controller#gpio-cellsgpio-rangeswakeup-parentgpio-reserved-rangespinsfunctiondrive-strengthbias-disableframe-numberqcom,tcs-offsetqcom,drv-idqcom,tcs-configqcom,pmic-idvdd-s1-supplyvdd-s2-supplyvdd-s3-supplyvdd-s4-supplyvdd-s5-supplyvdd-s6-supplyvdd-s7-supplyvdd-s8-supplyvdd-s9-supplyvdd-s10-supplyvdd-l1-l8-l11-supplyvdd-l2-l10-supplyvdd-l3-l4-l5-l18-supplyvdd-l6-l9-supplyvdd-l7-l12-l14-l15-supplyvdd-l13-l16-l17-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-initial-modevdd-l1-l8-supplyvdd-l2-l3-supplyvdd-l4-l5-l6-supplyvdd-l7-l11-supplyvdd-l9-l10-supplyvdd-bob-supplyvdd-l2-supplyvdd-l5-l6-supplyvdd-l7-supplypolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresisregulator-always-onregulator-boot-onvin-supply