t8x(@-hardkernel,rk3326-odroid-go2rockchip,rk3326 +7ODROID-GO Advancealiases=/ethernet@ff360000G/i2c@ff180000L/i2c@ff190000Q/i2c@ff1a0000V/i2c@ff1b0000[/serial@ff030000c/serial@ff158000k/serial@ff160000s/serial@ff168000{/serial@ff170000/serial@ff178000/spi@ff1d0000/spi@ff1d8000cpus+cpu@0cpuarm,cortex-a35psciZcpu@1cpuarm,cortex-a35psciZcpu@2cpuarm,cortex-a35psciZ cpu@3cpuarm,cortex-a35psciZ idle-statespscicpu-sleeparm,idle-state'8Ox`pcluster-sleeparm,idle-state'8O`pcpu0-opp-tableoperating-points-v2opp-600000000#F ~~p@opp-8160000000, p@opp-1008000000< p@opp-1200000000G   p@opp-1296000000M?d ppp@arm-pmuarm,cortex-a35-pmu0defg display-subsystemrockchip,display-subsystem okayexternal-gmac-clock fixed-clock gmac_clkin psci arm,psci-1.0smctimerarm,armv8-timer0   thermal-zonessoc-thermal/=O tripstrip-point-0_pkpassivetrip-point-1_Lkpassive soc-crit_8k criticalcooling-mapsmap0v  {map1v  {gpu-thermald/O xin24m fixed-clock n6xin24m]power-management@ff000000$rockchip,px30-pmusysconsimple-mfdpower-controllerrockchip,px30-power-controller+_pd_usb@5<pd_sdcard@7;pd_gmac@9  C@?pd_mmc_nand@10 @978:pd_vpu@11 Kpd_vo@12 XD56pd_vi@13 (3 !pd_gpu@14I"syscon@ff010000'rockchip,px30-pmugrfsysconsimple-mfd+yio-domains$rockchip,px30-pmu-io-voltage-domainokay##reboot-modesyscon-reboot-modeRBRB RBRB RBserial@ff030000$rockchip,px30-uartsnps,dw-apb-uart $$baudclkapb_pclk%%%*txrx4>Kdefault Y&'( disabledi2s@ff070000&rockchip,px30-i2srockchip,rk3066-i2s  i2s_clki2s_hclk%%%*txrxKdefaultY)*+,cokayi2s@ff080000&rockchip,px30-i2srockchip,rk3066-i2s i2s_clki2s_hclk%%%*txrxKdefaultY-./0c disabledinterrupt-controller@ff131000 arm,gic-400t@ @ `   syscon@ff140000$rockchip,px30-grfsysconsimple-mfd+4io-domains rockchip,px30-io-voltage-domainokay121111lvdsrockchip,px30-lvds3dphy4 lvds disabledports+port@0+endpoint@05xserial@ff158000$rockchip,px30-uartsnps,dw-apb-uart Ibaudclkapb_pclk%%%*txrx4>KdefaultY67okayserial@ff160000$rockchip,px30-uartsnps,dw-apb-uart Jbaudclkapb_pclk%%%*txrx4>KdefaultY8okayserial@ff168000$rockchip,px30-uartsnps,dw-apb-uart Kbaudclkapb_pclk%%%*txrx4>Kdefault Y9:; disabledserial@ff170000$rockchip,px30-uartsnps,dw-apb-uart Lbaudclkapb_pclk%%% *txrx4>Kdefault Y<=> disabledserial@ff178000$rockchip,px30-uartsnps,dw-apb-uart Mbaudclkapb_pclk%% % *txrx4>Kdefault Y?@A disabledi2c@ff180000&rockchip,px30-i2crockchip,rk3399-i2cN i2cpclk KdefaultYB+okay*Bpmic@20rockchip,rk817  C KdefaultYDYz rk808-clkout1xin32kEEEEEEEregulatorsDCDC_REG1 vdd_logic~0q0Doregulator-state-memVn~DCDC_REG2vdd_arm~pq0Dregulator-state-memn~DCDC_REG3vcc_ddr0Dregulator-state-memVDCDC_REG4vcc_3v32Z2Z0D1regulator-state-memn2ZLDO_REG2vcc_1v8w@w@0D\regulator-state-memVnw@LDO_REG3vdd_1v0B@B@0Dregulator-state-memVnB@LDO_REG4 vcc3v3_pmu2Z2Z0D#regulator-state-memVn2ZLDO_REG5 vccio_sdw@2Z0D2regulator-state-memVn2ZLDO_REG6vcc_sd2Z2ZDhregulator-state-memVn2ZLDO_REG7vcc_bl2Z2Zregulator-state-memn2ZLDO_REG8vcc_lcd**sregulator-state-memn*LDO_REG9vcc_cam--regulator-state-memn-i2c@ff190000&rockchip,px30-i2crockchip,rk3399-i2cO i2cpclk KdefaultYF+okayi2c@ff1a0000&rockchip,px30-i2crockchip,rk3399-i2cP i2cpclk  KdefaultYG+ disabledi2c@ff1b0000&rockchip,px30-i2crockchip,rk3399-i2c Q i2cpclk  KdefaultYH+ disabledspi@ff1d0000&rockchip,px30-spirockchip,rk3066-spi $Uspiclkapb_pclk%% % *txrxKdefaultYIJKL+ disabledspi@ff1d8000&rockchip,px30-spirockchip,rk3066-spi %Vspiclkapb_pclk%%%*txrxKdefaultYMNOPQ+ disabledwatchdog@ff1e0000 snps,dw-wdt[ % disabledpwm@ff200000&rockchip,px30-pwmrockchip,rk3328-pwm "S pwmpclkKdefaultYR disabledpwm@ff200010&rockchip,px30-pwmrockchip,rk3328-pwm "S pwmpclkKdefaultYSokaypwm@ff200020&rockchip,px30-pwmrockchip,rk3328-pwm "S pwmpclkKdefaultYT disabledpwm@ff200030&rockchip,px30-pwmrockchip,rk3328-pwm 0"S pwmpclkKdefaultYU disabledpwm@ff208000&rockchip,px30-pwmrockchip,rk3328-pwm #T pwmpclkKdefaultYV disabledpwm@ff208010&rockchip,px30-pwmrockchip,rk3328-pwm #T pwmpclkKdefaultYW disabledpwm@ff208020&rockchip,px30-pwmrockchip,rk3328-pwm #T pwmpclkKdefaultYX disabledpwm@ff208030&rockchip,px30-pwmrockchip,rk3328-pwm 0#T pwmpclkKdefaultYY disabledtimer@ff210000*rockchip,px30-timerrockchip,rk3288-timer! Y& pclktimerbus simple-bus+dmac@ff240000arm,pl330arm,primecell$@ apb_pclk%tsadc@ff280000rockchip,px30-tsadc( $,P,Xtsadcapb_pclk tsadc-apb4KinitdefaultsleepYZ&[0Z:okay saradc@ff288000,rockchip,px30-saradcrockchip,rk3399-saradc( TP-Wsaradcapb_pclk saradc-apbokayb\nvmem@ff290000rockchip,px30-otp)@/Zaotpapb_pclkphyphy+id@7cpu-leakage@17performance@1enclock-controller@ff2b0000rockchip,px30-cru+ ]$ xin24mgpll4 s@@I Fq рр f@clock-controller@ff2bc000rockchip,px30-pmucru+]xin24m4 s$$$ G$syscon@ff2c0000,rockchip,px30-usb2phy-grfsysconsimple-mfd,+usb2-phy@100rockchip,px30-usb2phy $ phyclk ^ usb480m_phyokay^host-port D linestateokayaotg-port$BA@otg-bvalidotg-idlinestate disabled`phy@ff2e0000rockchip,px30-dsi-dphy.$ E refpclk>apb_ okay3usb@ff3000000rockchip,px30-usbrockchip,rk3066-usbsnps,dwc20 >otgotg@ ` usb2-phy_okayusb@ff340000 generic-ehci4 <ausb_ disabledusb@ff350000 generic-ohci5 =ausb_ disabledethernet@ff360000rockchip,px30-gmac6 +macirq@>??@ACL[stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speed4rmiiKdefaultYbc_ ^ stmmaceth disabledmmc@ff370000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc7@ 6 ;CDbiuciuciu-driveciu-sample рKdefaultYdefg_okay$5 GCP]jwh2mmc@ff380000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc8@ 7 8EFbiuciuciu-driveciu-sample рKdefault Yijk_  disabledmmc@ff390000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc9@ 5 9GHbiuciuciu-driveciu-sample рKdefault Ylmn_  disabledgpu@ff400000$rockchip,px30-maliarm,mali-bifrost@@$/.- jobmmugpuI_okayodsi@ff450000rockchip,px30-mipi-dsiE KDpclk3dphy_ =apb4+okayports+port@0+endpoint@0pwport@1endpointqupanel@0elida,kd35t133rs tsportendpointuqvop@ff460000rockchip,px30-vop-bigF Maclk_vopdclk_vophclk_vop345 axiahbdclkv_ okayport+ endpoint@0wpendpoint@1x5iommu@ff460f00rockchip,iommuF M vopb_mmu aclkiface_ okayvqos@ff518000sysconQ qos@ff520000sysconR "qos@ff52c000sysconR qos@ff538000sysconS qos@ff538080sysconS qos@ff538100sysconS qos@ff538180sysconS qos@ff540000sysconT qos@ff540080sysconT qos@ff548000sysconT qos@ff548080sysconT qos@ff548100sysconT qos@ff548180sysconT  qos@ff548200sysconT !qos@ff550000sysconU qos@ff550080sysconU qos@ff550100sysconU qos@ff550180sysconU qos@ff558000sysconU qos@ff558080sysconU pinctrlrockchip,px30-pinctrl4y+gpio0@ff040000rockchip,gpio-bank $ tCgpio1@ff250000rockchip,gpio-bank% \ tgpio2@ff260000rockchip,gpio-bank& ] tgpio3@ff270000rockchip,gpio-bank' ^ ttpcfg-pull-up|pcfg-pull-down"pcfg-pull-none1{pcfg-pull-none-2ma1>pcfg-pull-up-2ma>pcfg-pull-up-4ma>}pcfg-pull-none-4ma1>pcfg-pull-down-4ma">pcfg-pull-none-8ma1>pcfg-pull-up-8ma>~pcfg-pull-none-12ma1> pcfg-pull-up-12ma> pcfg-pull-none-smt1Mzpcfg-output-highbpcfg-output-lownpcfg-input-highypcfg-inputyi2c0i2c0-xfer z zBi2c1i2c1-xfer zzFi2c2i2c2-xfer zzGi2c3i2c3-xfer  z zHtsadctsadc-otp-pin{Ztsadc-otp-out{[uart0uart0-xfer  | |&uart0-cts {'uart0-rts {(uart1uart1-xfer ||6uart1-cts{7uart1-rts{uart2-m0uart2m0-xfer ||uart2-m1uart2m1-xfer  ||8uart3-m0uart3m0-xfer ||uart3m0-cts{uart3m0-rts{uart3-m1uart3m1-xfer ||9uart3m1-cts {:uart3m1-rts {;uart4uart4-xfer ||<uart4-cts{=uart4-rts{>uart5uart5-xfer ||?uart5-cts{@uart5-rts{Aspi0spi0-clk}Ispi0-csn}Jspi0-miso }Kspi0-mosi }Lspi0-clk-hs~spi0-miso-hs ~spi0-mosi-hs ~spi1spi1-clk}Mspi1-csn0 }Nspi1-csn1 }Ospi1-miso}Pspi1-mosi }Qspi1-clk-hs~spi1-miso-hs~spi1-mosi-hs ~pdmpdm-clk0m0{pdm-clk0m1{pdm-clk1{pdm-sdi0m0{pdm-sdi0m1{pdm-sdi1{pdm-sdi2{pdm-sdi3{pdm-clk0m0-sleeppdm-clk0m1-sleeppdm-clk1-sleeppdm-sdi0m0-sleeppdm-sdi0m1-sleeppdm-sdi1-sleeppdm-sdi2-sleeppdm-sdi3-sleepi2s0i2s0-8ch-mclk{i2s0-8ch-sclktx{i2s0-8ch-sclkrx {i2s0-8ch-lrcktx{i2s0-8ch-lrckrx {i2s0-8ch-sdo0{i2s0-8ch-sdo1{i2s0-8ch-sdo2{i2s0-8ch-sdo3{i2s0-8ch-sdi0{i2s0-8ch-sdi1 {i2s0-8ch-sdi2 {i2s0-8ch-sdi3{i2s1i2s1-2ch-mclk{i2s1-2ch-sclk{)i2s1-2ch-lrck{*i2s1-2ch-sdi{+i2s1-2ch-sdo{,i2s2i2s2-2ch-mclk{i2s2-2ch-sclk{-i2s2-2ch-lrck{.i2s2-2ch-sdi{/i2s2-2ch-sdo{0sdmmcsdmmc-clkdsdmmc-cmd~esdmmc-det~fsdmmc-bus1~sdmmc-bus4@~~~~gsdiosdio-clk{ksdio-cmd|jsdio-bus4@||||iemmcemmc-clk lemmc-cmd ~memmc-rstnout {emmc-bus1~emmc-bus4@~~~~emmc-bus8~~~~~~~~nflashflash-cs0{flash-rdy {flash-dqs {flash-ale {flash-cle {flash-wrn {flash-csl{flash-rdn{flash-bus8lcdclcdc-rgb-dclk-pinlcdc-rgb-m0-hsync-pinlcdc-rgb-m0-vsync-pinlcdc-rgb-m0-den-pinlcdc-rgb888-m0-data-pins     lcdc-rgb666-m0-data-pins      lcdc-rgb565-m0-data-pins     lcdc-rgb888-m1-data-pins   lcdc-rgb666-m1-data-pins   lcdc-rgb565-m1-data-pins   pwm0pwm0-pin{Rpwm1pwm1-pin{Spwm2pwm2-pin {Tpwm3pwm3-pin{Upwm4pwm4-pin{Vpwm5pwm5-pin{Wpwm6pwm6-pin{Xpwm7pwm7-pin{Ygmacrmii-pins{{{{{ {bmac-refclk-12ma cmac-refclk {cif-m0cif-clkout-m0 {dvp-d2d9-m0{{{{{{{{{ { { {dvp-d0d1-m0  {{d10-d11-m0 {{cif-m1cif-clkout-m1{dvp-d2d9-m1{{{{ { {{{{{{{dvp-d0d1-m1 {{d10-d11-m1 {{ispisp-prelight{btnsbtn-pins|||| | |||||||||||headphonehp-detledsblue-led-pin{pmicdc-det {pmic-int |Dsoc_slppin_gpiosoc_slppin_rst{soc_slppin_slp{chosenserial2:115200n8backlightpwm-backlightargpio-keys gpio-keysKdefaultYsw1 J DPAD-UP sw2 J  DPAD-DOWN!sw3 J DPAD-LEFT"sw4 J DPAD-RIGHT#sw5 JBTN-A1sw6 JBTN-B0sw7 JBTN-Y4sw8 JBTN-X3sw9 JF1sw10 JF2sw11 JF3sw12 JF4sw13 JF5sw14 JF6sw15 J TOP-LEFT6sw16 J TOP-RIGHT7gpio-leds gpio-ledsKdefaultYled-0blue:heartbeat JC heartbeatvccsysregulator-fixed vcc3v8_sys099Evcc_hostregulator-fixed vcc_hostLK@LK@ C0E compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4serial5spi0spi1device_typeregenable-methodclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityportsstatusclock-frequencyclock-output-names#clock-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontribution#power-domain-cellspm_qospmuio1-supplypmuio2-supplyoffsetmode-bootloadermode-fastbootmode-loadermode-normalmode-recoveryclock-namesdmasdma-namesreg-shiftreg-io-widthpinctrl-namespinctrl-0#sound-dai-cells#interrupt-cellsinterrupt-controllervccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyphysphy-namesrockchip,grfrockchip,outputremote-endpointi2c-scl-falling-time-nsi2c-scl-rising-time-nsrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvoltregulator-off-in-suspend#pwm-cellsrangesarm,pl330-periph-burst#dma-cellsassigned-clocksassigned-clock-ratesresetsreset-namesrockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cells#io-channel-cellsvref-supplybits#reset-cellsassigned-clock-parents#phy-cellsinterrupt-namespower-domainsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy-modebus-widthfifo-depthmax-frequencycap-sd-highspeedcard-detect-delaycd-gpiossd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplymali-supplybacklightiovcc-supplyreset-gpiosvdd-supplyiommus#iommu-cellsrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathpower-supplypwmslabellinux,codelinux,default-triggergpioenable-active-highvin-supply